mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-18 12:29:21 +00:00
move FP into it's own select
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19867 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
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13c184de29
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40831c5e0e
@ -133,60 +133,47 @@ AlphaTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG)
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Alpha::F19, Alpha::F20, Alpha::F21};
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std::vector<unsigned> argVreg;
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std::vector<unsigned> argPreg;
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std::vector<unsigned> argOpc;
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int count = 0;
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for (Function::aiterator I = F.abegin(), E = F.aend(); I != E; ++I)
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{
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SDOperand newroot, argt;
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++count;
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assert(count <= 6 && "More than 6 args not supported");
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switch (getValueType(I->getType())) {
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default: std::cerr << "Unknown Type " << getValueType(I->getType()) << "\n"; abort();
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case MVT::f64:
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case MVT::f32:
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BuildMI(&BB, Alpha::IDEF, 0, args_float[count - 1]);
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argVreg.push_back(MF.getSSARegMap()->createVirtualRegister(getRegClassFor(getValueType(I->getType()))));
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argPreg.push_back(args_float[count - 1]);
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break;
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BuildMI(&BB, Alpha::IDEF, 0, args_float[count - 1]);
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argVreg.push_back(MF.getSSARegMap()->createVirtualRegister(getRegClassFor(getValueType(I->getType()))));
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argPreg.push_back(args_float[count - 1]);
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argOpc.push_back(Alpha::CPYS);
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newroot = DAG.getCopyFromReg(argVreg[count], getValueType(I->getType()), DAG.getRoot());
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break;
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case MVT::i1:
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case MVT::i8:
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case MVT::i16:
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case MVT::i32:
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case MVT::i64:
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BuildMI(&BB, Alpha::IDEF, 0, args_int[count - 1]);
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argVreg.push_back(MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64)));
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argPreg.push_back(args_int[count - 1]);
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break;
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}
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BuildMI(&BB, Alpha::IDEF, 0, args_int[count - 1]);
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argVreg.push_back(MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64)));
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argPreg.push_back(args_int[count - 1]);
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argOpc.push_back(Alpha::BIS);
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argt = newroot = DAG.getCopyFromReg(argVreg[count], MVT::i64, DAG.getRoot());
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if (getValueType(I->getType()) != MVT::i64)
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argt = DAG.getNode(ISD::TRUNCATE, getValueType(I->getType()), newroot);
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break;
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}
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DAG.setRoot(newroot.getValue(1));
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ArgValues.push_back(argt);
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}
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BuildMI(&BB, Alpha::IDEF, 0, Alpha::R29);
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BuildMI(&BB, Alpha::BIS, 2, GP).addReg(Alpha::R29).addReg(Alpha::R29);
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count = 0;
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for (Function::aiterator I = F.abegin(), E = F.aend(); I != E; ++I)
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{
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SDOperand newroot;
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unsigned Opc;
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switch (getValueType(I->getType()))
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{
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default: assert(0 && "Unhandled type");
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case MVT::i64:
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case MVT::i32:
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case MVT::i16:
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case MVT::i8:
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case MVT::i1:
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Opc = Alpha::BIS;
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break;
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case MVT::f32:
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case MVT::f64:
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Opc = Alpha::CPYS;
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break;
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}
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BuildMI(&BB, Opc, 2, argVreg[count]).addReg(argPreg[count]).addReg(argPreg[count]);
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newroot = DAG.getCopyFromReg(argVreg[count], getValueType(I->getType()), DAG.getRoot());
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DAG.setRoot(newroot.getValue(1));
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ArgValues.push_back(newroot);
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++count;
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}
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for (int i = 0; i < count; ++i)
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BuildMI(&BB, argOpc[i], 2, argVreg[i]).addReg(argPreg[i]).addReg(argPreg[i]);
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return ArgValues;
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}
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@ -209,19 +196,16 @@ AlphaTargetLowering::LowerCallTo(SDOperand Chain,
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// Promote the integer to 64 bits. If the input type is signed use a
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// sign extend, otherwise use a zero extend.
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if (Args[i].second->isSigned())
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Args[i].first = DAG.getNode(ISD::SIGN_EXTEND_INREG, MVT::i64, Args[i].first);
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Args[i].first = DAG.getNode(ISD::SIGN_EXTEND, MVT::i64, Args[i].first);
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else
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Args[i].first = DAG.getNode(ISD::ZERO_EXTEND_INREG, MVT::i64, Args[i].first);
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Args[i].first = DAG.getNode(ISD::ZERO_EXTEND, MVT::i64, Args[i].first);
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break;
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case MVT::i64:
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break;
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case MVT::f64:
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case MVT::f32:
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break;
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break;
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}
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args_to_use.push_back(Args[i].first);
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}
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std::vector<MVT::ValueType> RetVals;
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MVT::ValueType RetTyVT = getValueType(RetTy);
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if (RetTyVT != MVT::isVoid)
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@ -275,7 +259,6 @@ namespace {
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/// vreg the value is produced in, so we only emit one copy of each compiled
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/// tree.
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std::map<SDOperand, unsigned> ExprMap;
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std::set<SDOperand> LoweredTokens;
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public:
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ISel(TargetMachine &TM) : SelectionDAGISel(AlphaLowering), AlphaLowering(TM) {
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@ -289,20 +272,77 @@ namespace {
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// Clear state used for selection.
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ExprMap.clear();
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LoweredTokens.clear();
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}
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unsigned SelectExpr(SDOperand N);
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unsigned SelectExprFP(SDOperand N, unsigned Result);
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void Select(SDOperand N);
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};
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}
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unsigned ISel::SelectExprFP(SDOperand N, unsigned Result)
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{
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unsigned Tmp1, Tmp2, Tmp3;
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unsigned Opc = 0;
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SDNode *Node = N.Val;
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MVT::ValueType DestType = N.getValueType();
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unsigned opcode = N.getOpcode();
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switch (opcode) {
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default:
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Node->dump();
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assert(0 && "Node not handled!\n");
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case ISD::ConstantFP:
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if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N)) {
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if (CN->isExactlyValue(+0.0)) {
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BuildMI(BB, Alpha::CPYS, 2, Result).addReg(Alpha::F31).addReg(Alpha::F31);
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} else {
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abort();
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}
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}
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return Result;
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case ISD::MUL:
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case ISD::ADD:
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case ISD::SUB:
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case ISD::SDIV:
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switch( opcode ) {
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case ISD::MUL: Opc = DestType == MVT::f64 ? Alpha::MULT : Alpha::MULS; break;
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case ISD::ADD: Opc = DestType == MVT::f64 ? Alpha::ADDT : Alpha::ADDS; break;
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case ISD::SUB: Opc = DestType == MVT::f64 ? Alpha::SUBT : Alpha::SUBS; break;
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case ISD::SDIV: Opc = DestType == MVT::f64 ? Alpha::DIVT : Alpha::DIVS; break;
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};
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Tmp1 = SelectExpr(N.getOperand(0));
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Tmp2 = SelectExpr(N.getOperand(1));
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BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
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return Result;
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case ISD::SINT_TO_FP:
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{
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assert (N.getOperand(0).getValueType() == MVT::i64 && "only quads can be loaded from");
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Tmp1 = SelectExpr(N.getOperand(0)); // Get the operand register
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Tmp2 = MakeReg(DestType);
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//so these instructions are not supported on ev56
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Opc = DestType == MVT::f64 ? Alpha::ITOFT : Alpha::ITOFS;
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BuildMI(BB, Opc, 1, Tmp2).addReg(Tmp1);
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Opc = DestType == MVT::f64 ? Alpha::CVTQT : Alpha::CVTQS;
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BuildMI(BB, Opc, 1, Result).addReg(Tmp1);
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return Result;
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}
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}
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assert(0 && "should not get here");
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return 0;
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}
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unsigned ISel::SelectExpr(SDOperand N) {
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unsigned Result;
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unsigned Tmp1, Tmp2, Tmp3;
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unsigned Opc = 0;
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unsigned opcode = N.getOpcode();
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SDNode *Node = N.Val;
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MVT::ValueType DestType = N.getValueType();
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unsigned &Reg = ExprMap[N];
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if (Reg) return Reg;
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@ -324,22 +364,14 @@ unsigned ISel::SelectExpr(SDOperand N) {
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}
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}
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switch (N.getOpcode()) {
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if (DestType == MVT::f64 || DestType == MVT::f32)
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return SelectExprFP(N, Result);
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switch (opcode) {
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default:
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Node->dump();
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assert(0 && "Node not handled!\n");
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case ISD::ConstantFP:
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if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N)) {
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if (CN->isExactlyValue(+0.0) ||
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CN->isExactlyValue(-0.0)) {
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BuildMI(BB, Alpha::CPYS, 2, Result).addReg(Alpha::F31).addReg(Alpha::F31);
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} else {
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abort();
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}
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}
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return Result;
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case ISD::FrameIndex:
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Tmp1 = cast<FrameIndexSDNode>(N)->getIndex();
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BuildMI(BB, Alpha::LDA, 2, Result).addImm(Tmp1 * 8).addReg(Alpha::R30);
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@ -660,9 +692,12 @@ unsigned ISel::SelectExpr(SDOperand N) {
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case ISD::CopyFromReg:
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{
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if (Result == 1)
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// Make sure we generate both values.
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if (Result != 1)
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ExprMap[N.getValue(1)] = 1; // Generate the token
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else
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Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
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SDOperand Chain = N.getOperand(0);
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Select(Chain);
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@ -680,105 +715,73 @@ unsigned ISel::SelectExpr(SDOperand N) {
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case ISD::SHL:
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case ISD::SRL:
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case ISD::MUL:
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switch (N.getValueType()) {
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default: Node->dump(); assert (0 && "unhandled type");
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case MVT::f64:
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assert(N.getOpcode() == ISD::MUL && "only mul here please");
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Tmp1 = SelectExpr(N.getOperand(0));
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Tmp2 = SelectExpr(N.getOperand(1));
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BuildMI(BB, Alpha::MULT, 2, Result).addReg(Tmp1).addReg(Tmp2);
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break;
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case MVT::f32:
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assert(N.getOpcode() == ISD::MUL && "only mul here please");
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Tmp1 = SelectExpr(N.getOperand(0));
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Tmp2 = SelectExpr(N.getOperand(1));
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BuildMI(BB, Alpha::MULS, 2, Result).addReg(Tmp1).addReg(Tmp2);
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break;
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case MVT::i64:
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if(N.getOperand(1).getOpcode() == ISD::Constant &&
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cast<ConstantSDNode>(N.getOperand(1))->getValue() >= 0 &&
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cast<ConstantSDNode>(N.getOperand(1))->getValue() <= 255)
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{
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switch(N.getOpcode()) {
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case ISD::AND: Opc = Alpha::ANDi; break;
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case ISD::OR: Opc = Alpha::BISi; break;
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case ISD::XOR: Opc = Alpha::XORi; break;
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case ISD::SHL: Opc = Alpha::SLi; break;
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case ISD::SRL: Opc = Alpha::SRLi; break;
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case ISD::SRA: Opc = Alpha::SRAi; break;
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case ISD::MUL: Opc = Alpha::MULQi; break;
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};
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Tmp1 = SelectExpr(N.getOperand(0));
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Tmp2 = cast<ConstantSDNode>(N.getOperand(1))->getValue();
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BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addImm(Tmp2);
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}
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else
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{
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switch(N.getOpcode()) {
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case ISD::AND: Opc = Alpha::AND; break;
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case ISD::OR: Opc = Alpha::BIS; break;
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case ISD::XOR: Opc = Alpha::XOR; break;
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case ISD::SHL: Opc = Alpha::SL; break;
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case ISD::SRL: Opc = Alpha::SRL; break;
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case ISD::SRA: Opc = Alpha::SRA; break;
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case ISD::MUL: Opc = Alpha::MULQ; break;
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};
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Tmp1 = SelectExpr(N.getOperand(0));
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Tmp2 = SelectExpr(N.getOperand(1));
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BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
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}
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break;
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}
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assert (DestType == MVT::i64 && "Only do arithmetic on i64s!");
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if(N.getOperand(1).getOpcode() == ISD::Constant &&
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cast<ConstantSDNode>(N.getOperand(1))->getValue() >= 0 &&
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cast<ConstantSDNode>(N.getOperand(1))->getValue() <= 255)
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{
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switch(opcode) {
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case ISD::AND: Opc = Alpha::ANDi; break;
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case ISD::OR: Opc = Alpha::BISi; break;
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case ISD::XOR: Opc = Alpha::XORi; break;
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case ISD::SHL: Opc = Alpha::SLi; break;
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case ISD::SRL: Opc = Alpha::SRLi; break;
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case ISD::SRA: Opc = Alpha::SRAi; break;
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case ISD::MUL: Opc = Alpha::MULQi; break;
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};
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Tmp1 = SelectExpr(N.getOperand(0));
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Tmp2 = cast<ConstantSDNode>(N.getOperand(1))->getValue();
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BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addImm(Tmp2);
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}
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else
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{
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switch(opcode) {
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case ISD::AND: Opc = Alpha::AND; break;
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case ISD::OR: Opc = Alpha::BIS; break;
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case ISD::XOR: Opc = Alpha::XOR; break;
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case ISD::SHL: Opc = Alpha::SL; break;
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case ISD::SRL: Opc = Alpha::SRL; break;
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case ISD::SRA: Opc = Alpha::SRA; break;
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case ISD::MUL: Opc = Alpha::MULQ; break;
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};
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Tmp1 = SelectExpr(N.getOperand(0));
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Tmp2 = SelectExpr(N.getOperand(1));
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BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
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}
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return Result;
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case ISD::ADD:
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case ISD::SUB:
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{
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bool isAdd = N.getOpcode() == ISD::ADD;
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switch (N.getValueType()) {
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default: Node->dump(); assert(0 && "Unhandled type");
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case MVT::i64: {
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//FIXME: first check for Scaled Adds and Subs!
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if(N.getOperand(1).getOpcode() == ISD::Constant &&
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cast<ConstantSDNode>(N.getOperand(1))->getValue() >= 0 &&
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cast<ConstantSDNode>(N.getOperand(1))->getValue() <= 255)
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{ //Normal imm add/sub
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Opc = isAdd ? Alpha::ADDQi : Alpha::SUBQi;
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Tmp1 = SelectExpr(N.getOperand(0));
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Tmp2 = cast<ConstantSDNode>(N.getOperand(1))->getValue();
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BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addImm(Tmp2);
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}
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else if(N.getOperand(1).getOpcode() == ISD::Constant &&
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cast<ConstantSDNode>(N.getOperand(1))->getValue() >= 0 &&
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cast<ConstantSDNode>(N.getOperand(1))->getValue() <= 32767)
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{ //LDA //FIXME: expand the above condition a bit
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Tmp1 = SelectExpr(N.getOperand(0));
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Tmp2 = cast<ConstantSDNode>(N.getOperand(1))->getValue();
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if (!isAdd)
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Tmp2 = -Tmp2;
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BuildMI(BB, Alpha::LDA, 2, Result).addImm(Tmp2).addReg(Tmp1);
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}
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else
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{ //Normal add/sub
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Opc = isAdd ? Alpha::ADDQ : Alpha::SUBQ;
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Tmp1 = SelectExpr(N.getOperand(0));
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Tmp2 = SelectExpr(N.getOperand(1));
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BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
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}
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} break;
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case MVT::f64:
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case MVT::f32:
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if (N.getValueType() == MVT::f64)
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Opc = isAdd ? Alpha::ADDT : Alpha::SUBT;
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else
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Opc = isAdd ? Alpha::ADDS : Alpha::SUBS;
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//
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Tmp1 = SelectExpr(N.getOperand(0));
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Tmp2 = SelectExpr(N.getOperand(1));
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BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
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break;
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}
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bool isAdd = opcode == ISD::ADD;
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//FIXME: first check for Scaled Adds and Subs!
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if(N.getOperand(1).getOpcode() == ISD::Constant &&
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cast<ConstantSDNode>(N.getOperand(1))->getValue() >= 0 &&
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cast<ConstantSDNode>(N.getOperand(1))->getValue() <= 255)
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{ //Normal imm add/sub
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Opc = isAdd ? Alpha::ADDQi : Alpha::SUBQi;
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Tmp1 = SelectExpr(N.getOperand(0));
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Tmp2 = cast<ConstantSDNode>(N.getOperand(1))->getValue();
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BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addImm(Tmp2);
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}
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else if(N.getOperand(1).getOpcode() == ISD::Constant &&
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cast<ConstantSDNode>(N.getOperand(1))->getValue() >= 0 &&
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cast<ConstantSDNode>(N.getOperand(1))->getValue() <= 32767)
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{ //LDA //FIXME: expand the above condition a bit
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Tmp1 = SelectExpr(N.getOperand(0));
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Tmp2 = cast<ConstantSDNode>(N.getOperand(1))->getValue();
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if (!isAdd)
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Tmp2 = -Tmp2;
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BuildMI(BB, Alpha::LDA, 2, Result).addImm(Tmp2).addReg(Tmp1);
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}
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else
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{ //Normal add/sub
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||||
Opc = isAdd ? Alpha::ADDQ : Alpha::SUBQ;
|
||||
Tmp1 = SelectExpr(N.getOperand(0));
|
||||
Tmp2 = SelectExpr(N.getOperand(1));
|
||||
BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
|
||||
}
|
||||
return Result;
|
||||
}
|
||||
|
||||
@ -786,46 +789,19 @@ unsigned ISel::SelectExpr(SDOperand N) {
|
||||
case ISD::SREM:
|
||||
case ISD::SDIV:
|
||||
case ISD::UDIV:
|
||||
switch (N.getValueType()) {
|
||||
default: Node->dump(); assert (0 && "unhandled type");
|
||||
case MVT::f64:
|
||||
assert(N.getOpcode() == ISD::SDIV && "only div here please");
|
||||
Opc = Alpha::DIVT;
|
||||
break;
|
||||
case MVT::f32:
|
||||
assert(N.getOpcode() == ISD::SDIV && "only div here please");
|
||||
Opc = Alpha::DIVS;
|
||||
break;
|
||||
case MVT::i64:
|
||||
//FIXME: alpha really doesn't support any of these operations,
|
||||
// the ops are expanded into special library calls with
|
||||
// special calling conventions
|
||||
switch(N.getOpcode()) {
|
||||
case ISD::UREM: Opc = Alpha::REMQU; break;
|
||||
case ISD::SREM: Opc = Alpha::REMQ; break;
|
||||
case ISD::UDIV: Opc = Alpha::DIVQU; break;
|
||||
case ISD::SDIV: Opc = Alpha::DIVQ; break;
|
||||
}
|
||||
break;
|
||||
//FIXME: alpha really doesn't support any of these operations,
|
||||
// the ops are expanded into special library calls with
|
||||
// special calling conventions
|
||||
switch(opcode) {
|
||||
case ISD::UREM: Opc = Alpha::REMQU; break;
|
||||
case ISD::SREM: Opc = Alpha::REMQ; break;
|
||||
case ISD::UDIV: Opc = Alpha::DIVQU; break;
|
||||
case ISD::SDIV: Opc = Alpha::DIVQ; break;
|
||||
}
|
||||
Tmp1 = SelectExpr(N.getOperand(0));
|
||||
Tmp2 = SelectExpr(N.getOperand(1));
|
||||
BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
|
||||
return Result;
|
||||
|
||||
case ISD::SINT_TO_FP:
|
||||
{
|
||||
MVT::ValueType DestTy = N.getValueType();
|
||||
assert (N.getOperand(0).getValueType() == MVT::i64 && "only quads can be loaded from");
|
||||
Tmp1 = SelectExpr(N.getOperand(0)); // Get the operand register
|
||||
Tmp2 = MakeReg(DestTy);
|
||||
Opc = DestTy == MVT::f64 ? Alpha::ITOFT : Alpha::ITOFS;
|
||||
BuildMI(BB, Opc, 1, Tmp2).addReg(Tmp1);
|
||||
Opc = DestTy == MVT::f64 ? Alpha::CVTQT : Alpha::CVTQS;
|
||||
BuildMI(BB, Opc, 1, Result).addReg(Tmp1);
|
||||
return Result;
|
||||
}
|
||||
|
||||
// // case ISD::UINT_TO_FP:
|
||||
|
||||
// case ISD::FP_TO_SINT:
|
||||
@ -890,9 +866,9 @@ unsigned ISel::SelectExpr(SDOperand N) {
|
||||
void ISel::Select(SDOperand N) {
|
||||
unsigned Tmp1, Tmp2, Opc;
|
||||
|
||||
// FIXME: Disable for our current expansion model!
|
||||
if (/*!N->hasOneUse() &&*/ !LoweredTokens.insert(N).second)
|
||||
return; // Already selected.
|
||||
if(ExprMap[N])
|
||||
return; //alread selected
|
||||
ExprMap[N] = 1;
|
||||
|
||||
SDNode *Node = N.Val;
|
||||
|
||||
|
Loading…
Reference in New Issue
Block a user