Move isLoadFrom/StoreToStackSlot from MRegisterInfo to TargetInstrInfo,a far more logical place. Other methods should also be moved if anyoneis interested. :)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25913 91177308-0d34-0410-b5e6-96231b3b80d8

lib/CodeGen/VirtRegMap.cpp

@@ -490,8 +490,9 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, const VirtRegMap &VRM) {
       // straight load from the virt reg slot.
       if ((MR & VirtRegMap::isRef) && !(MR & VirtRegMap::isMod)) {
         int FrameIdx;
-        if (unsigned DestReg = MRI->isLoadFromStackSlot(&MI, FrameIdx)) {
+        if (unsigned DestReg = TII->isLoadFromStackSlot(&MI, FrameIdx)) {
-          // If this spill slot is available, insert a copy for it!
+          // If this spill slot is available, turn it into a copy (or nothing)
+          // instead of leaving it as a load!
           std::map<int, unsigned>::iterator It = SpillSlotsAvailable.find(SS);
           if (FrameIdx == SS && It != SpillSlotsAvailable.end()) {
             DEBUG(std::cerr << "Promoted Load To Copy: " << MI);

lib/Target/Alpha/AlphaInstrInfo.cpp

@@ -42,3 +42,22 @@ bool AlphaInstrInfo::isMoveInstr(const MachineInstr& MI,
   }
   return false;
 }
+
+unsigned 
+AlphaInstrInfo::isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const {
+  switch (MI->getOpcode()) {
+  case Alpha::LDL:
+  case Alpha::LDQ:
+  case Alpha::LDBU:
+  case Alpha::LDWU:
+  case Alpha::LDS:
+  case Alpha::LDT:
+    if (MI->getOperand(1).isFrameIndex()) {
+      FrameIndex = MI->getOperand(1).getFrameIndex();
+      return MI->getOperand(0).getReg();
+    }
+    break;
+  }
+  return 0;
+}
+

lib/Target/Alpha/AlphaInstrInfo.h

@@ -35,6 +35,8 @@ public:
   ///
   virtual bool isMoveInstr(const MachineInstr &MI,
                            unsigned &SrcReg, unsigned &DstReg) const;
+  
+  virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const;
 };
 
 }

lib/Target/Alpha/AlphaRegisterInfo.cpp

@@ -104,25 +104,6 @@ AlphaRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
     abort();
 }
 
-unsigned 
-AlphaRegisterInfo::isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const
-{
-  switch (MI->getOpcode()) {
-  case Alpha::LDL:
-  case Alpha::LDQ:
-  case Alpha::LDBU:
-  case Alpha::LDWU:
-  case Alpha::LDS:
-  case Alpha::LDT:
-    if (MI->getOperand(1).isFrameIndex()) {
-      FrameIndex = MI->getOperand(1).getFrameIndex();
-      return MI->getOperand(0).getReg();
-    }
-    break;
-  }
-  return 0;
-}
-
 MachineInstr *AlphaRegisterInfo::foldMemoryOperand(MachineInstr *MI,
                                                  unsigned OpNum,
                                                  int FrameIndex) const {

lib/Target/Alpha/AlphaRegisterInfo.h

@@ -35,8 +35,6 @@ struct AlphaRegisterInfo : public AlphaGenRegisterInfo {
                             unsigned DestReg, int FrameIndex,
                             const TargetRegisterClass *RC) const;
   
-  virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const;
-
   MachineInstr* foldMemoryOperand(MachineInstr *MI, unsigned OpNum, 
                                   int FrameIndex) const;
 

lib/Target/PowerPC/PPCInstrInfo.cpp

@@ -79,6 +79,25 @@ bool PPCInstrInfo::isMoveInstr(const MachineInstr& MI,
   return false;
 }
 
+unsigned PPCInstrInfo::isLoadFromStackSlot(MachineInstr *MI, 
+                                              int &FrameIndex) const {
+  switch (MI->getOpcode()) {
+  default: break;
+  case PPC::LD:
+  case PPC::LWZ:
+  case PPC::LFS:
+  case PPC::LFD:
+    if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImmedValue() &&
+        MI->getOperand(2).isFrameIndex()) {
+      FrameIndex = MI->getOperand(2).getFrameIndex();
+      return MI->getOperand(0).getReg();
+    }
+    break;
+  }
+  return 0;
+                                              }
+
+
 // commuteInstruction - We can commute rlwimi instructions, but only if the
 // rotate amt is zero.  We also have to munge the immediates a bit.
 MachineInstr *PPCInstrInfo::commuteInstruction(MachineInstr *MI) const {

lib/Target/PowerPC/PPCInstrInfo.h

@@ -39,6 +39,8 @@ public:
                            unsigned& sourceReg,
                            unsigned& destReg) const;
 
+  unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const;
+
   // commuteInstruction - We can commute rlwimi instructions, but only if the
   // rotate amt is zero.  We also have to munge the immediates a bit.
   virtual MachineInstr *commuteInstruction(MachineInstr *MI) const;

lib/Target/PowerPC/PPCRegisterInfo.cpp

@@ -116,24 +116,6 @@ void PPCRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
   }
 }
 
-unsigned PPCRegisterInfo::isLoadFromStackSlot(MachineInstr *MI, 
-                                              int &FrameIndex) const {
-  switch (MI->getOpcode()) {
-  default: break;
-  case PPC::LD:
-  case PPC::LWZ:
-  case PPC::LFS:
-  case PPC::LFD:
-    if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImmedValue() &&
-        MI->getOperand(2).isFrameIndex()) {
-      FrameIndex = MI->getOperand(2).getFrameIndex();
-      return MI->getOperand(0).getReg();
-    }
-    break;
-  }
-  return 0;
-}
-
 /// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into
 /// copy instructions, turning them into load/store instructions.
 MachineInstr *PPCRegisterInfo::foldMemoryOperand(MachineInstr *MI,

lib/Target/PowerPC/PPCRegisterInfo.h

@@ -42,8 +42,6 @@ public:
                     unsigned DestReg, unsigned SrcReg,
                     const TargetRegisterClass *RC) const;
 
-  unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const;
-    
   /// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into
   /// copy instructions, turning them into load/store instructions.
   virtual MachineInstr* foldMemoryOperand(MachineInstr* MI, unsigned OpNum,

lib/Target/X86/X86InstrInfo.cpp

@@ -41,6 +41,54 @@ bool X86InstrInfo::isMoveInstr(const MachineInstr& MI,
   return false;
 }
 
+unsigned X86InstrInfo::isLoadFromStackSlot(MachineInstr *MI, 
+                                           int &FrameIndex) const {
+  switch (MI->getOpcode()) {
+  default: break;
+  case X86::MOV8rm:
+  case X86::MOV16rm:
+  case X86::MOV32rm:
+  case X86::FpLD64m:
+  case X86::MOVSSrm:
+  case X86::MOVSDrm:
+    if (MI->getOperand(1).isFrameIndex() && MI->getOperand(2).isImmediate() &&
+        MI->getOperand(3).isRegister() && MI->getOperand(4).isImmediate() &&
+        MI->getOperand(2).getImmedValue() == 1 &&
+        MI->getOperand(3).getReg() == 0 &&
+        MI->getOperand(4).getImmedValue() == 0) {
+      FrameIndex = MI->getOperand(1).getFrameIndex();
+      return MI->getOperand(0).getReg();
+    }
+    break;
+  }
+  return 0;
+}
+
+unsigned X86InstrInfo::isStoreToStackSlot(MachineInstr *MI,
+                                          int &FrameIndex) const {
+  switch (MI->getOpcode()) {
+  default: break;
+  case X86::MOV8mr:
+  case X86::MOV16mr:
+  case X86::MOV32mr:
+  case X86::FpSTP64m:
+  case X86::MOVSSmr:
+  case X86::MOVSDmr:
+    if (MI->getOperand(0).isFrameIndex() && MI->getOperand(1).isImmediate() &&
+        MI->getOperand(2).isRegister() && MI->getOperand(3).isImmediate() &&
+        MI->getOperand(3).getImmedValue() == 1 &&
+        MI->getOperand(4).getReg() == 0 &&
+        MI->getOperand(5).getImmedValue() == 0) {
+      FrameIndex = MI->getOperand(1).getFrameIndex();
+      return MI->getOperand(4).getReg();
+    }
+    break;
+  }
+  return 0;
+}
+
+
+
 /// convertToThreeAddress - This method must be implemented by targets that
 /// set the M_CONVERTIBLE_TO_3_ADDR flag.  When this flag is set, the target
 /// may be able to convert a two-address instruction into a true

lib/Target/X86/X86InstrInfo.h

@@ -179,13 +179,13 @@ public:
   ///
   virtual const MRegisterInfo &getRegisterInfo() const { return RI; }
 
-  //
   // Return true if the instruction is a register to register move and
   // leave the source and dest operands in the passed parameters.
   //
-  virtual bool isMoveInstr(const MachineInstr& MI,
+  bool isMoveInstr(const MachineInstr& MI, unsigned& sourceReg,
-                           unsigned& sourceReg,
+                   unsigned& destReg) const;
-                           unsigned& destReg) const;
+  unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const;
+  unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const;
   
   /// convertToThreeAddress - This method must be implemented by targets that
   /// set the M_CONVERTIBLE_TO_3_ADDR flag.  When this flag is set, the target

lib/Target/X86/X86RegisterInfo.cpp

@@ -116,52 +116,6 @@ void X86RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
   BuildMI(MBB, MI, Opc, 1, DestReg).addReg(SrcReg);
 }
 
-unsigned X86RegisterInfo::isLoadFromStackSlot(MachineInstr *MI, 
-                                              int &FrameIndex) const {
-  switch (MI->getOpcode()) {
-  default: break;
-  case X86::MOV8rm:
-  case X86::MOV16rm:
-  case X86::MOV32rm:
-  case X86::FpLD64m:
-  case X86::MOVSSrm:
-  case X86::MOVSDrm:
-    if (MI->getOperand(1).isFrameIndex() && MI->getOperand(2).isImmediate() &&
-        MI->getOperand(3).isRegister() && MI->getOperand(4).isImmediate() &&
-        MI->getOperand(2).getImmedValue() == 1 &&
-        MI->getOperand(3).getReg() == 0 &&
-        MI->getOperand(4).getImmedValue() == 0) {
-      FrameIndex = MI->getOperand(1).getFrameIndex();
-      return MI->getOperand(0).getReg();
-    }
-    break;
-  }
-  return 0;
-}
-
-unsigned X86RegisterInfo::isStoreToStackSlot(MachineInstr *MI, 
-                                             int &FrameIndex) const {
-  switch (MI->getOpcode()) {
-  default: break;
-  case X86::MOV8mr:
-  case X86::MOV16mr:
-  case X86::MOV32mr:
-  case X86::FpSTP64m:
-  case X86::MOVSSmr:
-  case X86::MOVSDmr:
-    if (MI->getOperand(0).isFrameIndex() && MI->getOperand(1).isImmediate() &&
-        MI->getOperand(2).isRegister() && MI->getOperand(3).isImmediate() &&
-        MI->getOperand(3).getImmedValue() == 1 &&
-        MI->getOperand(4).getReg() == 0 &&
-        MI->getOperand(5).getImmedValue() == 0) {
-      FrameIndex = MI->getOperand(1).getFrameIndex();
-      return MI->getOperand(4).getReg();
-    }
-    break;
-  }
-  return 0;
-}
-
 
 static MachineInstr *MakeMInst(unsigned Opcode, unsigned FrameIndex,
                                MachineInstr *MI) {

lib/Target/X86/X86RegisterInfo.h

@@ -41,10 +41,6 @@ struct X86RegisterInfo : public X86GenRegisterInfo {
                     unsigned DestReg, unsigned SrcReg,
                     const TargetRegisterClass *RC) const;
 
-  unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const;
-  unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const;
-
-
   /// foldMemoryOperand - If this target supports it, fold a load or store of
   /// the specified stack slot into the specified machine instruction for the
   /// specified operand.  If this is possible, the target should perform the