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FastISel support for ConstantExprs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55843 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -61,6 +61,13 @@ public:
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///
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///
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bool SelectInstruction(Instruction *I);
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bool SelectInstruction(Instruction *I);
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/// SelectInstruction - Do "fast" instruction selection for the given
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/// LLVM IR operator (Instruction or ConstantExpr), and append
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/// generated machine instructions to the current block. Return true
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/// if selection was successful.
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///
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bool SelectOperator(User *I, unsigned Opcode);
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/// TargetSelectInstruction - This method is called by target-independent
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/// TargetSelectInstruction - This method is called by target-independent
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/// code when the normal FastISel process fails to select an instruction.
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/// code when the normal FastISel process fails to select an instruction.
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/// This gives targets a chance to emit code for anything that doesn't
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/// This gives targets a chance to emit code for anything that doesn't
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@ -226,13 +233,13 @@ protected:
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}
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}
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private:
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private:
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bool SelectBinaryOp(Instruction *I, ISD::NodeType ISDOpcode);
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bool SelectBinaryOp(User *I, ISD::NodeType ISDOpcode);
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bool SelectGetElementPtr(Instruction *I);
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bool SelectGetElementPtr(User *I);
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bool SelectBitCast(Instruction *I);
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bool SelectBitCast(User *I);
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bool SelectCast(Instruction *I, ISD::NodeType Opcode);
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bool SelectCast(User *I, ISD::NodeType Opcode);
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};
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};
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}
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}
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@ -63,6 +63,9 @@ unsigned FastISel::getRegForValue(Value *V) {
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if (Reg == 0)
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if (Reg == 0)
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return 0;
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return 0;
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}
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}
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} else if (ConstantExpr *CE = dyn_cast<ConstantExpr>(V)) {
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if (!SelectOperator(CE, CE->getOpcode())) return 0;
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Reg = LocalValueMap[CE];
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} else if (isa<UndefValue>(V)) {
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} else if (isa<UndefValue>(V)) {
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Reg = createResultReg(TLI.getRegClassFor(VT));
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Reg = createResultReg(TLI.getRegClassFor(VT));
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BuildMI(MBB, TII.get(TargetInstrInfo::IMPLICIT_DEF), Reg);
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BuildMI(MBB, TII.get(TargetInstrInfo::IMPLICIT_DEF), Reg);
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@ -81,6 +84,10 @@ unsigned FastISel::getRegForValue(Value *V) {
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/// a value before we select the block that defines the value. It might be
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/// a value before we select the block that defines the value. It might be
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/// possible to fix this by selecting blocks in reverse postorder.
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/// possible to fix this by selecting blocks in reverse postorder.
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void FastISel::UpdateValueMap(Value* I, unsigned Reg) {
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void FastISel::UpdateValueMap(Value* I, unsigned Reg) {
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if (!isa<Instruction>(I)) {
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LocalValueMap[I] = Reg;
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return;
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}
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if (!ValueMap.count(I))
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if (!ValueMap.count(I))
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ValueMap[I] = Reg;
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ValueMap[I] = Reg;
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else
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else
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@ -91,7 +98,7 @@ void FastISel::UpdateValueMap(Value* I, unsigned Reg) {
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/// SelectBinaryOp - Select and emit code for a binary operator instruction,
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/// SelectBinaryOp - Select and emit code for a binary operator instruction,
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/// which has an opcode which directly corresponds to the given ISD opcode.
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/// which has an opcode which directly corresponds to the given ISD opcode.
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///
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///
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bool FastISel::SelectBinaryOp(Instruction *I, ISD::NodeType ISDOpcode) {
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bool FastISel::SelectBinaryOp(User *I, ISD::NodeType ISDOpcode) {
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MVT VT = MVT::getMVT(I->getType(), /*HandleUnknown=*/true);
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MVT VT = MVT::getMVT(I->getType(), /*HandleUnknown=*/true);
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if (VT == MVT::Other || !VT.isSimple())
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if (VT == MVT::Other || !VT.isSimple())
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// Unhandled type. Halt "fast" selection and bail.
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// Unhandled type. Halt "fast" selection and bail.
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@ -148,7 +155,7 @@ bool FastISel::SelectBinaryOp(Instruction *I, ISD::NodeType ISDOpcode) {
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return true;
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return true;
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}
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}
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bool FastISel::SelectGetElementPtr(Instruction *I) {
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bool FastISel::SelectGetElementPtr(User *I) {
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unsigned N = getRegForValue(I->getOperand(0));
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unsigned N = getRegForValue(I->getOperand(0));
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if (N == 0)
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if (N == 0)
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// Unhandled operand. Halt "fast" selection and bail.
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// Unhandled operand. Halt "fast" selection and bail.
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@ -223,7 +230,7 @@ bool FastISel::SelectGetElementPtr(Instruction *I) {
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return true;
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return true;
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}
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}
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bool FastISel::SelectCast(Instruction *I, ISD::NodeType Opcode) {
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bool FastISel::SelectCast(User *I, ISD::NodeType Opcode) {
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MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
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MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
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MVT DstVT = TLI.getValueType(I->getType());
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MVT DstVT = TLI.getValueType(I->getType());
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@ -249,7 +256,7 @@ bool FastISel::SelectCast(Instruction *I, ISD::NodeType Opcode) {
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return true;
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return true;
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}
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}
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bool FastISel::SelectBitCast(Instruction *I) {
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bool FastISel::SelectBitCast(User *I) {
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// If the bitcast doesn't change the type, just use the operand value.
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// If the bitcast doesn't change the type, just use the operand value.
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if (I->getType() == I->getOperand(0)->getType()) {
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if (I->getType() == I->getOperand(0)->getType()) {
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unsigned Reg = getRegForValue(I->getOperand(0));
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unsigned Reg = getRegForValue(I->getOperand(0));
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@ -301,7 +308,12 @@ bool FastISel::SelectBitCast(Instruction *I) {
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bool
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bool
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FastISel::SelectInstruction(Instruction *I) {
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FastISel::SelectInstruction(Instruction *I) {
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switch (I->getOpcode()) {
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return SelectOperator(I, I->getOpcode());
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}
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bool
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FastISel::SelectOperator(User *I, unsigned Opcode) {
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switch (Opcode) {
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case Instruction::Add: {
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case Instruction::Add: {
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ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FADD : ISD::ADD;
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ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FADD : ISD::ADD;
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return SelectBinaryOp(I, Opc);
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return SelectBinaryOp(I, Opc);
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