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Teach SimplifySetCC that comparing AssertZext i1 against a constant 1 can be rewritten as a compare against a constant 0 with the opposite condition.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170495 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -2206,7 +2206,8 @@ TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
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Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ;
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return DAG.getSetCC(dl, VT, Op0.getOperand(0), Op0.getOperand(1),
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Cond);
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} else if (Op0.getOpcode() == ISD::AND &&
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}
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if (Op0.getOpcode() == ISD::AND &&
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isa<ConstantSDNode>(Op0.getOperand(1)) &&
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cast<ConstantSDNode>(Op0.getOperand(1))->getAPIntValue() == 1) {
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// If this is (X&1) == / != 1, normalize it to (X&1) != / == 0.
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@ -2223,6 +2224,11 @@ TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
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DAG.getConstant(0, Op0.getValueType()),
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Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
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}
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if (Op0.getOpcode() == ISD::AssertZext &&
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cast<VTSDNode>(Op0.getOperand(1))->getVT() == MVT::i1)
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return DAG.getSetCC(dl, VT, Op0,
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DAG.getConstant(0, Op0.getValueType()),
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Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
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}
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}
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@ -151,3 +151,18 @@ entry:
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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}
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define i32 @test12() uwtable ssp {
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; CHECK: test12:
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; CHECK: testb
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%1 = call zeroext i1 @test12b()
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br i1 %1, label %2, label %3
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; <label>:2 ; preds = %0
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ret i32 1
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; <label>:3 ; preds = %0
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ret i32 2
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}
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declare zeroext i1 @test12b()
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