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Sanity check the option operand for DMB/DSB.

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PR9648
rdar://problem/9257634


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129146 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Johnny Chen 2011-04-08 19:18:07 +00:00
parent 5b03a3a59a
commit 40de2b3f15
5 changed files with 67 additions and 8 deletions
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18
lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
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@ -3286,13 +3286,19 @@ static bool DisassembleMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
if (MemBarrierInstr(insn)) {
// DMBsy, DSBsy, and ISBsy instructions have zero operand and are taken care
// of within the generic ARMBasicMCBuilder::BuildIt() method.
//
// Inst{3-0} encodes the memory barrier option for the variants.
MI.addOperand(MCOperand::CreateImm(slice(insn, 3, 0)));
NumOpsAdded = 1;
return true;
unsigned opt = slice(insn, 3, 0);
switch (opt) {
case ARM_MB::SY: case ARM_MB::ST:
case ARM_MB::ISH: case ARM_MB::ISHST:
case ARM_MB::NSH: case ARM_MB::NSHST:
case ARM_MB::OSH: case ARM_MB::OSHST:
MI.addOperand(MCOperand::CreateImm(opt));
NumOpsAdded = 1;
return true;
default:
return false;
}
}
switch (Opcode) {

19
lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h
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@ -1616,8 +1616,7 @@ static inline bool t2MiscCtrlInstr(uint32_t insn) {
// A8.6.26
// t2BXJ -> Rn
//
// Miscellaneous control: t2DMBsy (and its t2DMB variants),
// t2DSBsy (and its t2DSB varianst), t2ISBsy, t2CLREX
// Miscellaneous control:
// -> no operand (except pred-imm pred-ccr for CLREX, memory barrier variants)
//
// Hint: t2NOP, t2YIELD, t2WFE, t2WFI, t2SEV
@ -1634,6 +1633,22 @@ static bool DisassembleThumb2BrMiscCtrl(MCInst &MI, unsigned Opcode,
if (NumOps == 0)
return true;
if (Opcode == ARM::t2DMB || Opcode == ARM::t2DSB) {
// Inst{3-0} encodes the memory barrier option for the variants.
unsigned opt = slice(insn, 3, 0);
switch (opt) {
case ARM_MB::SY: case ARM_MB::ST:
case ARM_MB::ISH: case ARM_MB::ISHST:
case ARM_MB::NSH: case ARM_MB::NSHST:
case ARM_MB::OSH: case ARM_MB::OSHST:
MI.addOperand(MCOperand::CreateImm(opt));
NumOpsAdded = 1;
return true;
default:
return false;
}
}
if (t2MiscCtrlInstr(insn))
return true;

16
test/MC/Disassembler/ARM/invalid-DMB-thumb.txt Normal file
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@ -0,0 +1,16 @@
# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding}
# Opcode=1908 Name=t2DMB Format=ARM_FORMAT_THUMBFRM(25)
# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
# -------------------------------------------------------------------------------------------------
# | 1: 1: 1: 1| 0: 0: 1: 1| 1: 0: 1: 1| 1: 1: 1: 1| 1: 0: 0: 0| 1: 1: 1: 1| 0: 1: 0: 1| 0: 0: 0: 1|
# -------------------------------------------------------------------------------------------------
#
# Inst{3-0} encodes the option: SY, ST, ISH, ISHST, NSH, NSHST, OSH, OSHST.
# Reject invalid encodings.
#
# See also A8.6.42 DSB
# All other encodings of option are reserved. It is IMPLEMENTATION DEFINED whether options
# other than SY are implemented. All unsupported and reserved options must execute as a full
# system DSB operation, but software must not rely on this behavior.
0xbf 0xf3 0x51 0x8f

16
test/MC/Disassembler/ARM/invalid-DSB-arm.txt Normal file
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@ -0,0 +1,16 @@
# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding}
# Opcode=102 Name=DSB Format=ARM_FORMAT_MISCFRM(26)
# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
# -------------------------------------------------------------------------------------------------
# | 1: 1: 1: 1| 0: 1: 0: 1| 0: 1: 1: 1| 1: 1: 1: 1| 1: 1: 1: 1| 0: 0: 0: 0| 0: 1: 0: 0| 0: 0: 0: 0|
# -------------------------------------------------------------------------------------------------
#
# Inst{3-0} encodes the option: SY, ST, ISH, ISHST, NSH, NSHST, OSH, OSHST.
# Reject invalid encodings.
#
# See also A8.6.42 DSB
# All other encodings of option are reserved. It is IMPLEMENTATION DEFINED whether options
# other than SY are implemented. All unsupported and reserved options must execute as a full
# system DSB operation, but software must not rely on this behavior.
0x40 0xf0 0x7f 0xf5

6
test/MC/Disassembler/ARM/thumb-tests.txt
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@ -202,3 +202,9 @@
# CHECK: vmov r1, r0, d11
0x50 0xec 0x1b 0x1b
# CHECK: dsb nsh
0xbf 0xf3 0x47 0x8f
# CHECK: isb
0xbf 0xf3 0x6f 0x8f