diff --git a/lib/Target/Mips/Mips.td b/lib/Target/Mips/Mips.td index 11efe45af52..40f5b938e22 100644 --- a/lib/Target/Mips/Mips.td +++ b/lib/Target/Mips/Mips.td @@ -81,8 +81,6 @@ def FeatureSwap : SubtargetFeature<"swap", "HasSwap", "true", "Enable 'byte/half swap' instructions.">; def FeatureBitCount : SubtargetFeature<"bitcount", "HasBitCount", "true", "Enable 'count leading bits' instructions.">; -def FeatureFPIdx : SubtargetFeature<"fpidx", "HasFPIdx", "true", - "Enable 'FP indexed load/store' instructions.">; def FeatureMips1 : SubtargetFeature<"mips1", "MipsArchVersion", "Mips1", "Mips I ISA Support [highly experimental]">; def FeatureMips2 : SubtargetFeature<"mips2", "MipsArchVersion", "Mips2", @@ -98,10 +96,13 @@ def FeatureMips3 : SubtargetFeature<"mips3", "MipsArchVersion", "Mips3", def FeatureMips4_32 : SubtargetFeature<"mips4_32", "HasMips4_32", "true", "Subset of MIPS-IV that is also in MIPS32 " "[highly experimental]">; +def FeatureMips4_32r2 : SubtargetFeature<"mips4_32r2", "HasMips4_32r2", "true", + "Subset of MIPS-IV that is also in MIPS32r2 " + "[highly experimental]">; def FeatureMips4 : SubtargetFeature<"mips4", "MipsArchVersion", "Mips4", "MIPS IV ISA Support", [FeatureMips3, FeatureMips4_32, - FeatureFPIdx]>; + FeatureMips4_32r2]>; def FeatureMips5 : SubtargetFeature<"mips5", "MipsArchVersion", "Mips5", "MIPS V ISA Support [highly experimental]", [FeatureMips4]>; @@ -111,8 +112,8 @@ def FeatureMips32 : SubtargetFeature<"mips32", "MipsArchVersion", "Mips32", FeatureMips4_32, FeatureBitCount]>; def FeatureMips32r2 : SubtargetFeature<"mips32r2", "MipsArchVersion", "Mips32r2", "Mips32r2 ISA Support", - [FeatureMips32, FeatureSEInReg, FeatureSwap, - FeatureFPIdx]>; + [FeatureMips4_32r2, FeatureMips32, + FeatureSEInReg, FeatureSwap]>; def FeatureMips32r6 : SubtargetFeature<"mips32r6", "MipsArchVersion", "Mips32r6", "Mips32r6 ISA Support [experimental]", @@ -120,7 +121,7 @@ def FeatureMips32r6 : SubtargetFeature<"mips32r6", "MipsArchVersion", FeatureNaN2008]>; def FeatureMips64 : SubtargetFeature<"mips64", "MipsArchVersion", "Mips64", "Mips64 ISA Support", - [FeatureMips5, FeatureMips32, FeatureFPIdx]>; + [FeatureMips5, FeatureMips32]>; def FeatureMips64r2 : SubtargetFeature<"mips64r2", "MipsArchVersion", "Mips64r2", "Mips64r2 ISA Support", [FeatureMips64, FeatureMips32r2]>; diff --git a/lib/Target/Mips/Mips16ISelDAGToDAG.cpp b/lib/Target/Mips/Mips16ISelDAGToDAG.cpp index 92b9e6d74f1..4e86a27e323 100644 --- a/lib/Target/Mips/Mips16ISelDAGToDAG.cpp +++ b/lib/Target/Mips/Mips16ISelDAGToDAG.cpp @@ -225,10 +225,12 @@ bool Mips16DAGToDAGISel::selectAddr16( // If an indexed floating point load/store can be emitted, return false. const LSBaseSDNode *LS = dyn_cast(Parent); - if (LS && - (LS->getMemoryVT() == MVT::f32 || LS->getMemoryVT() == MVT::f64) && - Subtarget.hasFPIdx()) - return false; + if (LS) { + if (LS->getMemoryVT() == MVT::f32 && Subtarget.hasMips4_32r2()) + return false; + if (LS->getMemoryVT() == MVT::f64 && Subtarget.hasMips4_32r2()) + return false; + } } Base = Addr; Offset = CurDAG->getTargetConstant(0, ValTy); diff --git a/lib/Target/Mips/MipsInstrFPU.td b/lib/Target/Mips/MipsInstrFPU.td index 5f4376ad012..8f9d25ecc10 100644 --- a/lib/Target/Mips/MipsInstrFPU.td +++ b/lib/Target/Mips/MipsInstrFPU.td @@ -406,23 +406,25 @@ def SDC3 : SW_FT<"sdc3", COP3Opnd, NoItinerary, store>, LW_FM<0x3f>, ISA_MIPS2; // Indexed loads and stores. // Base register + offset register addressing mode (indicated by "x" in the // instruction mnemonic) is disallowed under NaCl. -let AdditionalPredicates = [IsNotNaCl, HasFPIdx] in { - def LWXC1 : MMRel, LWXC1_FT<"lwxc1", FGR32Opnd, II_LWXC1, load>, LWXC1_FM<0>; - def SWXC1 : MMRel, SWXC1_FT<"swxc1", FGR32Opnd, II_SWXC1, store>, SWXC1_FM<8>; +let AdditionalPredicates = [IsNotNaCl] in { + def LWXC1 : MMRel, LWXC1_FT<"lwxc1", FGR32Opnd, II_LWXC1, load>, LWXC1_FM<0>, + INSN_MIPS4_32R2; + def SWXC1 : MMRel, SWXC1_FT<"swxc1", FGR32Opnd, II_SWXC1, store>, SWXC1_FM<8>, + INSN_MIPS4_32R2; } -let AdditionalPredicates = [HasFPIdx, NotInMicroMips, IsNotNaCl] in { +let AdditionalPredicates = [NotInMicroMips, IsNotNaCl] in { def LDXC1 : LWXC1_FT<"ldxc1", AFGR64Opnd, II_LDXC1, load>, LWXC1_FM<1>, - FGR_32; + INSN_MIPS4_32R2, FGR_32; def SDXC1 : SWXC1_FT<"sdxc1", AFGR64Opnd, II_SDXC1, store>, SWXC1_FM<9>, - FGR_32; + INSN_MIPS4_32R2, FGR_32; } -let AdditionalPredicates = [HasFPIdx], DecoderNamespace="Mips64" in { +let DecoderNamespace="Mips64" in { def LDXC164 : LWXC1_FT<"ldxc1", FGR64Opnd, II_LDXC1, load>, LWXC1_FM<1>, - FGR_64; + INSN_MIPS4_32R2, FGR_64; def SDXC164 : SWXC1_FT<"sdxc1", FGR64Opnd, II_SDXC1, store>, SWXC1_FM<9>, - FGR_64; + INSN_MIPS4_32R2, FGR_64; } // Load/store doubleword indexed unaligned. diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td index 540cd230ea5..9a3945a7f77 100644 --- a/lib/Target/Mips/MipsInstrInfo.td +++ b/lib/Target/Mips/MipsInstrInfo.td @@ -152,8 +152,6 @@ def HasBitCount : Predicate<"Subtarget.hasBitCount()">, AssemblerPredicate<"FeatureBitCount">; def HasSwap : Predicate<"Subtarget.hasSwap()">, AssemblerPredicate<"FeatureSwap">; -def HasFPIdx : Predicate<"Subtarget.hasFPIdx()">, - AssemblerPredicate<"FeatureFPIdx">; def HasMips2 : Predicate<"Subtarget.hasMips2()">, AssemblerPredicate<"FeatureMips2">; def HasMips3_32 : Predicate<"Subtarget.hasMips3_32()">, @@ -162,6 +160,8 @@ def HasMips3 : Predicate<"Subtarget.hasMips3()">, AssemblerPredicate<"FeatureMips3">; def HasMips4_32 : Predicate<"Subtarget.hasMips4_32()">, AssemblerPredicate<"FeatureMips4_32">; +def HasMips4_32r2 : Predicate<"Subtarget.hasMips4_32r2()">, + AssemblerPredicate<"FeatureMips4_32r2">; def HasMips32 : Predicate<"Subtarget.hasMips32()">, AssemblerPredicate<"FeatureMips32">; def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">, @@ -223,6 +223,9 @@ class INSN_MIPS3_32 { list InsnPredicates = [HasMips3_32]; } // The portions of MIPS-IV that were also added to MIPS32 class INSN_MIPS4_32 { list InsnPredicates = [HasMips4_32]; } +// The portions of MIPS-IV that were also added to MIPS32R2 +class INSN_MIPS4_32R2 { list InsnPredicates = [HasMips4_32r2]; } + class INSN_SWAP { list InsnPredicates = [HasSwap]; } class INSN_SEINREG { list InsnPredicates = [HasSEInReg]; } diff --git a/lib/Target/Mips/MipsSubtarget.cpp b/lib/Target/Mips/MipsSubtarget.cpp index 6624f1dec4d..b19ef652641 100644 --- a/lib/Target/Mips/MipsSubtarget.cpp +++ b/lib/Target/Mips/MipsSubtarget.cpp @@ -81,11 +81,12 @@ MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU, MipsABI(UnknownABI), IsLittle(little), IsSingleFloat(false), IsFP64bit(false), IsNaN2008bit(false), IsGP64bit(false), HasVFPU(false), HasCnMips(false), IsLinux(true), HasMips3_32(false), HasMips4_32(false), - HasSEInReg(false), HasSwap(false), HasBitCount(false), HasFPIdx(false), - InMips16Mode(false), InMips16HardFloat(Mips16HardFloat), - InMicroMipsMode(false), HasDSP(false), HasDSPR2(false), - AllowMixed16_32(Mixed16_32 | Mips_Os16), Os16(Mips_Os16), HasMSA(false), - RM(_RM), OverrideMode(NoOverride), TM(_TM), TargetTriple(TT) { + HasMips4_32r2(false), HasSEInReg(false), HasSwap(false), + HasBitCount(false), InMips16Mode(false), + InMips16HardFloat(Mips16HardFloat), InMicroMipsMode(false), HasDSP(false), + HasDSPR2(false), AllowMixed16_32(Mixed16_32 | Mips_Os16), Os16(Mips_Os16), + HasMSA(false), RM(_RM), OverrideMode(NoOverride), TM(_TM), + TargetTriple(TT) { std::string CPUName = CPU; CPUName = selectMipsCPU(TT, CPUName); diff --git a/lib/Target/Mips/MipsSubtarget.h b/lib/Target/Mips/MipsSubtarget.h index cf7adff23e1..aa69110e447 100644 --- a/lib/Target/Mips/MipsSubtarget.h +++ b/lib/Target/Mips/MipsSubtarget.h @@ -82,9 +82,12 @@ protected: // HasMips3_32 - The subset of MIPS-III instructions added to MIPS32 bool HasMips3_32; - // HasMips4_32 - The subset of MIPS-IV instructions added to MIPS32 + // HasMips4_32 - Has the subset of MIPS-IV present in MIPS32 bool HasMips4_32; + // HasMips4_32r2 - Has the subset of MIPS-IV present in MIPS32r2 + bool HasMips4_32r2; + // HasSEInReg - SEB and SEH (signext in register) instructions. bool HasSEInReg; @@ -94,9 +97,6 @@ protected: // HasBitCount - Count leading '1' and '0' bits. bool HasBitCount; - // HasFPIdx -- Floating point indexed load/store instructions. - bool HasFPIdx; - // InMips16 -- can process Mips16 instructions bool InMips16Mode; @@ -160,6 +160,7 @@ public: bool hasMips2() const { return MipsArchVersion >= Mips2; } bool hasMips3() const { return MipsArchVersion >= Mips3; } bool hasMips4_32() const { return HasMips4_32; } + bool hasMips4_32r2() const { return HasMips4_32r2; } bool hasMips32() const { return MipsArchVersion >= Mips32; } bool hasMips32r2() const { return MipsArchVersion == Mips32r2 || MipsArchVersion == Mips64r2; } @@ -216,7 +217,6 @@ public: bool hasSEInReg() const { return HasSEInReg; } bool hasSwap() const { return HasSwap; } bool hasBitCount() const { return HasBitCount; } - bool hasFPIdx() const { return HasFPIdx; } bool hasExtractInsert() const { return !inMips16Mode() && hasMips32r2(); } const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }