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Make the implicit inputs and outputs of target-independent

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ADDC/ADDE use MVT::i1 (later, whatever it gets legalized to)
instead of MVT::Flag.  Remove CARRY_FALSE in favor of 0; adjust
all target-independent code to use this format.

Most targets will still produce a Flag-setting target-dependent
version when selection is done.  X86 is converted to use i32
instead, which means TableGen needs to produce different code
in xxxGenDAGISel.inc.  This keys off the new supportsHasI1 bit
in xxxInstrInfo, currently set only for X86; in principle this
is temporary and should go away when all other targets have
been converted.  All relevant X86 instruction patterns are
modified to represent setting and using EFLAGS explicitly.  The
same can be done on other targets.

The immediate behavior change is that an ADC/ADD pair are no
longer tightly coupled in the X86 scheduler; they can be
separated by instructions that don't clobber the flags (MOV).
I will soon add some peephole optimizations based on using
other instructions that set the flags to feed into ADC.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72707 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dale Johannesen
2009-06-01 23:27:20 +00:00
parent 8313899851
commit 4150d83abe
17 changed files with 431 additions and 124 deletions
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8
include/llvm/CodeGen/SelectionDAG.h
View File

@@ -324,6 +324,14 @@ public:
return getNode(ISD::CopyToReg, dl, MVT::Other, Chain,
getRegister(Reg, N.getValueType()), N);
}
// This version of getCopyToReg has the register (and its type) as an
// explicit output.
SDValue getCopyToReg(SDValue Chain, DebugLoc dl, MVT VT, unsigned Reg,
SDValue N) {
SDVTList VTs = getVTList(MVT::Other, VT);
SDValue Ops[] = { Chain, getRegister(Reg, VT), N};
return getNode(ISD::CopyToReg, dl, VTs, Ops, 3);
}
// This version of the getCopyToReg method takes an extra operand, which
// indicates that there is potentially an incoming flag value (if Flag is not

10
include/llvm/CodeGen/SelectionDAGNodes.h
View File

@@ -242,14 +242,11 @@ namespace ISD {
// remainder result.
SDIVREM, UDIVREM,
// CARRY_FALSE - This node is used when folding other nodes,
// like ADDC/SUBC, which indicate the carry result is always false.
CARRY_FALSE,
// Carry-setting nodes for multiple precision addition and subtraction.
// These nodes take two operands of the same value type, and produce two
// results. The first result is the normal add or sub result, the second
// result is the carry flag result.
// result is the carry flag result (type i1 or whatever it got expanded to
// for the target, value 0 or 1).
ADDC, SUBC,
// Carry-using nodes for multiple precision addition and subtraction. These
@@ -258,7 +255,8 @@ namespace ISD {
// produce two results; the normal result of the add or sub, and the output
// carry flag. These nodes both read and write a carry flag to allow them
// to them to be chained together for add and sub of arbitrarily large
// values.
// values. The carry flag (input and output) has type i1 or whatever it
// got expanded to for the target, and has value 0 or 1.
ADDE, SUBE,
// RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition.