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Make the implicit inputs and outputs of target-independent

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ADDC/ADDE use MVT::i1 (later, whatever it gets legalized to)
instead of MVT::Flag.  Remove CARRY_FALSE in favor of 0; adjust
all target-independent code to use this format.

Most targets will still produce a Flag-setting target-dependent
version when selection is done.  X86 is converted to use i32
instead, which means TableGen needs to produce different code
in xxxGenDAGISel.inc.  This keys off the new supportsHasI1 bit
in xxxInstrInfo, currently set only for X86; in principle this
is temporary and should go away when all other targets have
been converted.  All relevant X86 instruction patterns are
modified to represent setting and using EFLAGS explicitly.  The
same can be done on other targets.

The immediate behavior change is that an ADC/ADD pair are no
longer tightly coupled in the X86 scheduler; they can be
separated by instructions that don't clobber the flags (MOV).
I will soon add some peephole optimizations based on using
other instructions that set the flags to feed into ADC.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72707 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dale Johannesen
2009-06-01 23:27:20 +00:00
parent 8313899851
commit 4150d83abe
17 changed files with 431 additions and 124 deletions
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5
include/llvm/Target/Target.td
View File

@@ -326,6 +326,11 @@ class InstrInfo {
// Sparc manual specifies its instructions in the format [31..0] (big), while
// PowerPC specifies them using the format [0..31] (little).
bit isLittleEndianEncoding = 0;
// Targets that can support the HasI1 argument on ADDC and ADDE, rather than
// Flag, have this bit set. This is transitional and should go away when all
// targets have been switched over.
bit supportsHasI1 = 0;
}
// Standard Instructions.

10
include/llvm/Target/TargetSelectionDAG.td
View File

@@ -216,6 +216,8 @@ def SDNPMayStore : SDNodeProperty; // May write to memory, sets 'mayStore'.
def SDNPMayLoad : SDNodeProperty; // May read memory, sets 'mayLoad'.
def SDNPSideEffect : SDNodeProperty; // Sets 'HasUnmodelledSideEffects'.
def SDNPMemOperand : SDNodeProperty; // Touches memory, has assoc MemOperand
def SDNPInI1 : SDNodeProperty; // Read an extra I1 operand
def SDNPOutI1 : SDNodeProperty; // Write an extra I1 result
//===----------------------------------------------------------------------===//
// Selection DAG Node definitions.
@@ -289,13 +291,13 @@ def or : SDNode<"ISD::OR" , SDTIntBinOp,
def xor : SDNode<"ISD::XOR" , SDTIntBinOp,
[SDNPCommutative, SDNPAssociative]>;
def addc : SDNode<"ISD::ADDC" , SDTIntBinOp,
[SDNPCommutative, SDNPOutFlag]>;
[SDNPCommutative, SDNPOutI1]>;
def adde : SDNode<"ISD::ADDE" , SDTIntBinOp,
[SDNPCommutative, SDNPOutFlag, SDNPInFlag]>;
[SDNPCommutative, SDNPInI1, SDNPOutI1]>;
def subc : SDNode<"ISD::SUBC" , SDTIntBinOp,
[SDNPOutFlag]>;
[SDNPOutI1]>;
def sube : SDNode<"ISD::SUBE" , SDTIntBinOp,
[SDNPOutFlag, SDNPInFlag]>;
[SDNPInI1, SDNPOutI1]>;
def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>;
def bswap : SDNode<"ISD::BSWAP" , SDTIntUnaryOp>;