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- Treat a live range defined by an implicit_def as a zero-sized one.

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- Eliminate an implicit_def when it's being spilled.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49166 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2008-04-03 16:39:43 +00:00
parent 576a27043d
commit 419852ca8a
2 changed files with 32 additions and 2 deletions
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4
include/llvm/CodeGen/LiveIntervalAnalysis.h
View File

@ -394,6 +394,10 @@ namespace llvm {
BitVector &RestoreMBBs, BitVector &RestoreMBBs,
std::map<unsigned,std::vector<SRInfo> >&RestoreIdxes); std::map<unsigned,std::vector<SRInfo> >&RestoreIdxes);
/// removeSpilledImpDefs - Remove IMPLICIT_DEF instructions which are being
/// spilled.
void removeSpilledImpDefs(const LiveInterval &li, VirtRegMap &vrm);
/// rewriteImplicitOps - Rewrite implicit use operands of MI (i.e. uses of /// rewriteImplicitOps - Rewrite implicit use operands of MI (i.e. uses of
/// interval on to-be re-materialized operands of MI) with new register. /// interval on to-be re-materialized operands of MI) with new register.
void rewriteImplicitOps(const LiveInterval &li, void rewriteImplicitOps(const LiveInterval &li,

30
lib/CodeGen/LiveIntervalAnalysis.cpp
View File

@ -201,6 +201,11 @@ void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb,
DOUT << "\t\tregister: "; DEBUG(printRegName(interval.reg)); DOUT << "\t\tregister: "; DEBUG(printRegName(interval.reg));
LiveVariables::VarInfo& vi = lv_->getVarInfo(interval.reg); LiveVariables::VarInfo& vi = lv_->getVarInfo(interval.reg);
if (mi->getOpcode() == TargetInstrInfo::IMPLICIT_DEF) {
DOUT << "is a implicit_def\n";
return;
}
// Virtual registers may be defined multiple times (due to phi // Virtual registers may be defined multiple times (due to phi
// elimination and 2-addr elimination). Much of what we do only has to be // elimination and 2-addr elimination). Much of what we do only has to be
// done once for the vreg. We use an empty interval to detect the first // done once for the vreg. We use an empty interval to detect the first
@ -1105,7 +1110,7 @@ rewriteInstructionsForSpills(const LiveInterval &li, bool TrySplit,
std::vector<RewriteInfo> RewriteMIs; std::vector<RewriteInfo> RewriteMIs;
for (MachineRegisterInfo::reg_iterator ri = mri_->reg_begin(li.reg), for (MachineRegisterInfo::reg_iterator ri = mri_->reg_begin(li.reg),
re = mri_->reg_end(); ri != re; ) { re = mri_->reg_end(); ri != re; ) {
MachineInstr *MI = &(*ri); MachineInstr *MI = &*ri;
MachineOperand &O = ri.getOperand(); MachineOperand &O = ri.getOperand();
++ri; ++ri;
assert(!O.isImplicit() && "Spilling register that's used as implicit use?"); assert(!O.isImplicit() && "Spilling register that's used as implicit use?");
@ -1307,6 +1312,22 @@ void LiveIntervals::eraseRestoreInfo(int Id, int index, unsigned vr,
Restores[i].index = -1; Restores[i].index = -1;
} }
/// removeSpilledImpDefs - Remove IMPLICIT_DEF instructions which are being
/// spilled.
void LiveIntervals::removeSpilledImpDefs(const LiveInterval &li,
VirtRegMap &vrm) {
for (MachineRegisterInfo::reg_iterator ri = mri_->reg_begin(li.reg),
re = mri_->reg_end(); ri != re; ) {
MachineInstr *MI = &*ri;
++ri;
if (MI->getOpcode() != TargetInstrInfo::IMPLICIT_DEF)
continue;
RemoveMachineInstrFromMaps(MI);
vrm.RemoveMachineInstrFromMaps(MI);
MI->eraseFromParent();
}
}
std::vector<LiveInterval*> LiveIntervals:: std::vector<LiveInterval*> LiveIntervals::
addIntervalsForSpills(const LiveInterval &li, addIntervalsForSpills(const LiveInterval &li,
@ -1386,6 +1407,8 @@ addIntervalsForSpills(const LiveInterval &li,
} }
IsFirstRange = false; IsFirstRange = false;
} }
removeSpilledImpDefs(li, vrm);
return NewLIs; return NewLIs;
} }
@ -1454,8 +1477,10 @@ addIntervalsForSpills(const LiveInterval &li,
} }
// Insert spills / restores if we are splitting. // Insert spills / restores if we are splitting.
if (!TrySplit) if (!TrySplit) {
removeSpilledImpDefs(li, vrm);
return NewLIs; return NewLIs;
}
SmallPtrSet<LiveInterval*, 4> AddedKill; SmallPtrSet<LiveInterval*, 4> AddedKill;
SmallVector<unsigned, 2> Ops; SmallVector<unsigned, 2> Ops;
@ -1608,6 +1633,7 @@ addIntervalsForSpills(const LiveInterval &li,
} }
} }
removeSpilledImpDefs(li, vrm);
return RetNewLIs; return RetNewLIs;
} }