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[Hexagon] Replacing old version of convert and load f64.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226057 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Colin LeMahieu 2015-01-14 23:07:36 +00:00
parent 8f9d11309a
commit 419855bfeb
5 changed files with 22 additions and 23 deletions
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10
lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
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@ -79,6 +79,8 @@ public:
bool SelectADDRriU6_1(SDValue& N, SDValue &R1, SDValue &R2);
bool SelectADDRriU6_2(SDValue& N, SDValue &R1, SDValue &R2);
bool SelectAddrFI(SDValue &N, SDValue &R);
const char *getPassName() const override {
return "Hexagon DAG->DAG Pattern Instruction Selection";
}
@ -1683,3 +1685,11 @@ bool HexagonDAGToDAGISel::foldGlobalAddressImpl(SDValue &N, SDValue &R,
}
return false;
}
bool HexagonDAGToDAGISel::SelectAddrFI(SDValue& N, SDValue &R) {
if (N.getOpcode() != ISD::FrameIndex)
return false;
FrameIndexSDNode *FX = cast<FrameIndexSDNode>(N);
R = CurDAG->getTargetFrameIndex(FX->getIndex(), MVT::i32);
return true;
}

1
lib/Target/Hexagon/HexagonInstrInfo.cpp
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@ -1101,7 +1101,6 @@ isValidOffset(const int Opcode, const int Offset) const {
(Offset <= Hexagon_MEMW_OFFSET_MAX);
case Hexagon::L2_loadrd_io:
case Hexagon::LDrid_f:
case Hexagon::S2_storerd_io:
case Hexagon::STrid_f:
return (Offset >= Hexagon_MEMD_OFFSET_MIN) &&

9
lib/Target/Hexagon/HexagonInstrInfo.td
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@ -1558,6 +1558,15 @@ defm loadri: LD_Idxd <"memw", "LDriw", IntRegs, s11_2Ext, u6_2Ext, 0b1100>;
let accessSize = DoubleWordAccess, opExtentAlign = 3, isCodeGenOnly = 0 in
defm loadrd: LD_Idxd <"memd", "LDrid", DoubleRegs, s11_3Ext, u6_3Ext, 0b1110>;
// Patterns to select load-indexed (i.e. load from base+offset).
multiclass Loadx_pat<PatFrag Load, ValueType VT, PatLeaf ImmPred,
InstHexagon MI> {
def: Pat<(VT (Load AddrFI:$fi)), (VT (MI AddrFI:$fi, 0))>;
def: Pat<(VT (Load (add (i32 IntRegs:$Rs), ImmPred:$Off))),
(VT (MI IntRegs:$Rs, imm:$Off))>;
def: Pat<(VT (Load (i32 IntRegs:$Rs))), (VT (MI IntRegs:$Rs, 0))>;
}
def : Pat < (i32 (sextloadi8 ADDRriS11_0:$addr)),
(L2_loadrb_io AddrFI:$addr, 0) >;

22
lib/Target/Hexagon/HexagonInstrInfoV5.td
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@ -112,6 +112,8 @@ def S5_popcountp : ALU64_rr<(outs IntRegs:$Rd), (ins DoubleRegs:$Rss),
let Inst{20-16} = Rss;
}
defm: Loadx_pat<load, f64, s11_3ExtPred, L2_loadrd_io>;
let isFP = 1, hasNewValue = 1, opNewValue = 0 in
class T_MInstFloat <string mnemonic, bits<3> MajOp, bits<3> MinOp>
: MInst<(outs IntRegs:$Rd),
@ -483,26 +485,6 @@ def F2_dfimm_p : T_fimm <"dfmake", DoubleRegs, 0b1001, 0>;
def F2_dfimm_n : T_fimm <"dfmake", DoubleRegs, 0b1001, 1>;
}
// Convert single precision to double precision and vice-versa.
def CONVERT_sf2df : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src),
"$dst = convert_sf2df($src)",
[(set DoubleRegs:$dst, (fextend IntRegs:$src))]>,
Requires<[HasV5T]>;
def CONVERT_df2sf : ALU64_rr<(outs IntRegs:$dst), (ins DoubleRegs:$src),
"$dst = convert_df2sf($src)",
[(set IntRegs:$dst, (fround DoubleRegs:$src))]>,
Requires<[HasV5T]>;
// Load.
def LDrid_f : LDInst<(outs DoubleRegs:$dst),
(ins MEMri:$addr),
"$dst = memd($addr)",
[(set DoubleRegs:$dst, (f64 (load ADDRriS11_3:$addr)))]>,
Requires<[HasV5T]>;
let AddedComplexity = 20 in
def LDrid_indexed_f : LDInst<(outs DoubleRegs:$dst),
(ins IntRegs:$src1, s11_3Imm:$offset),

3
lib/Target/Hexagon/HexagonRegisterInfo.cpp
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@ -165,8 +165,7 @@ void HexagonRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
(MI.getOpcode() == Hexagon::L2_loadruh_io) ||
(MI.getOpcode() == Hexagon::L2_loadrb_io) ||
(MI.getOpcode() == Hexagon::L2_loadrub_io) ||
(MI.getOpcode() == Hexagon::LDriw_f) ||
(MI.getOpcode() == Hexagon::LDrid_f)) {
(MI.getOpcode() == Hexagon::LDriw_f)) {
unsigned dstReg = (MI.getOpcode() == Hexagon::L2_loadrd_io) ?
getSubReg(MI.getOperand(0).getReg(), Hexagon::subreg_loreg) :
MI.getOperand(0).getReg();