From 419f3804f0912521c2ed4de83124542234456ce3 Mon Sep 17 00:00:00 2001 From: Joerg Sonnenberger Date: Sat, 2 Aug 2014 15:09:41 +0000 Subject: [PATCH] Don't use additional arguments for dss and friends to satisfy DSS_Form, when let can do the same thing. Keep the 64bit variants as codegen-only. While they have a different register class, the encoding is the same for 32bit and 64bit mode. Having both present would otherwise confuse the disassembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214636 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/PowerPC/PPCInstrAltivec.td | 114 ++++++++---------- lib/Target/PowerPC/PPCInstrFormats.td | 3 +- .../PowerPC/ppc64-encoding-ext.txt | 13 ++ test/MC/PowerPC/ppc64-encoding-ext.s | 20 +++ 4 files changed, 87 insertions(+), 63 deletions(-) diff --git a/lib/Target/PowerPC/PPCInstrAltivec.td b/lib/Target/PowerPC/PPCInstrAltivec.td index 0924cd8bb1b..33d3a7e4715 100644 --- a/lib/Target/PowerPC/PPCInstrAltivec.td +++ b/lib/Target/PowerPC/PPCInstrAltivec.td @@ -258,48 +258,64 @@ class VX2_Int_Ty2 xo, string opc, Intrinsic IntID, ValueType OutTy, def HasAltivec : Predicate<"PPCSubTarget->hasAltivec()">; let Predicates = [HasAltivec] in { -let isCodeGenOnly = 1 in { -def DSS : DSS_Form<822, (outs), - (ins u5imm:$ZERO0, u5imm:$STRM,u5imm:$ZERO1,u5imm:$ZERO2), - "dss $STRM", IIC_LdStLoad /*FIXME*/, []>, - Deprecated; -def DSSALL : DSS_Form<822, (outs), - (ins u5imm:$ONE, u5imm:$ZERO0,u5imm:$ZERO1,u5imm:$ZERO2), - "dssall", IIC_LdStLoad /*FIXME*/, []>, - Deprecated; -def DST : DSS_Form<342, (outs), - (ins u5imm:$ZERO, u5imm:$STRM, gprc:$rA, gprc:$rB), - "dst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, []>, - Deprecated; -def DSTT : DSS_Form<342, (outs), - (ins u5imm:$ONE, u5imm:$STRM, gprc:$rA, gprc:$rB), - "dstt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, []>, - Deprecated; -def DSTST : DSS_Form<374, (outs), - (ins u5imm:$ZERO, u5imm:$STRM, gprc:$rA, gprc:$rB), - "dstst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, []>, - Deprecated; -def DSTSTT : DSS_Form<374, (outs), - (ins u5imm:$ONE, u5imm:$STRM, gprc:$rA, gprc:$rB), - "dststt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, []>, +def DSS : DSS_Form<0, 822, (outs), (ins u5imm:$STRM), + "dss $STRM", IIC_LdStLoad /*FIXME*/, [(int_ppc_altivec_dss imm:$STRM)]>, + Deprecated { + let A = 0; + let B = 0; +} + +def DSSALL : DSS_Form<1, 822, (outs), (ins), + "dssall", IIC_LdStLoad /*FIXME*/, [(int_ppc_altivec_dssall)]>, + Deprecated { + let STRM = 0; + let A = 0; + let B = 0; +} + +def DST : DSS_Form<0, 342, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB), + "dst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, + [(int_ppc_altivec_dst i32:$rA, i32:$rB, imm:$STRM)]>, Deprecated; -def DST64 : DSS_Form<342, (outs), - (ins u5imm:$ZERO, u5imm:$STRM, g8rc:$rA, gprc:$rB), - "dst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, []>, +def DSTT : DSS_Form<1, 342, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB), + "dstt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, + [(int_ppc_altivec_dstt i32:$rA, i32:$rB, imm:$STRM)]>, Deprecated; -def DSTT64 : DSS_Form<342, (outs), - (ins u5imm:$ONE, u5imm:$STRM, g8rc:$rA, gprc:$rB), - "dstt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, []>, + +def DSTST : DSS_Form<0, 374, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB), + "dstst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, + [(int_ppc_altivec_dstst i32:$rA, i32:$rB, imm:$STRM)]>, Deprecated; -def DSTST64 : DSS_Form<374, (outs), - (ins u5imm:$ZERO, u5imm:$STRM, g8rc:$rA, gprc:$rB), - "dstst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, []>, - Deprecated; -def DSTSTT64 : DSS_Form<374, (outs), - (ins u5imm:$ONE, u5imm:$STRM, g8rc:$rA, gprc:$rB), - "dststt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, []>, + +def DSTSTT : DSS_Form<1, 374, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB), + "dststt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, + [(int_ppc_altivec_dststt i32:$rA, i32:$rB, imm:$STRM)]>, Deprecated; + +let isCodeGenOnly = 1 in { + // The very same instructions as above, but formally matching 64bit registers. + def DST64 : DSS_Form<0, 342, (outs), (ins u5imm:$STRM, g8rc:$rA, gprc:$rB), + "dst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, + [(int_ppc_altivec_dst i64:$rA, i32:$rB, imm:$STRM)]>, + Deprecated; + + def DSTT64 : DSS_Form<1, 342, (outs), (ins u5imm:$STRM, g8rc:$rA, gprc:$rB), + "dstt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, + [(int_ppc_altivec_dstt i64:$rA, i32:$rB, imm:$STRM)]>, + Deprecated; + + def DSTST64 : DSS_Form<0, 374, (outs), (ins u5imm:$STRM, g8rc:$rA, gprc:$rB), + "dstst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, + [(int_ppc_altivec_dstst i64:$rA, i32:$rB, + imm:$STRM)]>, + Deprecated; + + def DSTSTT64 : DSS_Form<1, 374, (outs), (ins u5imm:$STRM, g8rc:$rA, gprc:$rB), + "dststt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, + [(int_ppc_altivec_dststt i64:$rA, i32:$rB, + imm:$STRM)]>, + Deprecated; } def MFVSCR : VXForm_4<1540, (outs vrrc:$vD), (ins), @@ -747,30 +763,6 @@ def V_SETALLONES : VXForm_3<908, (outs vrrc:$vD), (ins), // Additional Altivec Patterns // -// DS* intrinsics -def : Pat<(int_ppc_altivec_dssall), (DSSALL 1, 0, 0, 0)>; -def : Pat<(int_ppc_altivec_dss imm:$STRM), (DSS 0, imm:$STRM, 0, 0)>; - -// * 32-bit -def : Pat<(int_ppc_altivec_dst i32:$rA, i32:$rB, imm:$STRM), - (DST 0, imm:$STRM, $rA, $rB)>; -def : Pat<(int_ppc_altivec_dstt i32:$rA, i32:$rB, imm:$STRM), - (DSTT 1, imm:$STRM, $rA, $rB)>; -def : Pat<(int_ppc_altivec_dstst i32:$rA, i32:$rB, imm:$STRM), - (DSTST 0, imm:$STRM, $rA, $rB)>; -def : Pat<(int_ppc_altivec_dststt i32:$rA, i32:$rB, imm:$STRM), - (DSTSTT 1, imm:$STRM, $rA, $rB)>; - -// * 64-bit -def : Pat<(int_ppc_altivec_dst i64:$rA, i32:$rB, imm:$STRM), - (DST64 0, imm:$STRM, $rA, $rB)>; -def : Pat<(int_ppc_altivec_dstt i64:$rA, i32:$rB, imm:$STRM), - (DSTT64 1, imm:$STRM, $rA, $rB)>; -def : Pat<(int_ppc_altivec_dstst i64:$rA, i32:$rB, imm:$STRM), - (DSTST64 0, imm:$STRM, $rA, $rB)>; -def : Pat<(int_ppc_altivec_dststt i64:$rA, i32:$rB, imm:$STRM), - (DSTSTT64 1, imm:$STRM, $rA, $rB)>; - // Loads. def : Pat<(v4i32 (load xoaddr:$src)), (LVX xoaddr:$src)>; diff --git a/lib/Target/PowerPC/PPCInstrFormats.td b/lib/Target/PowerPC/PPCInstrFormats.td index 18d77cdd803..8a5a60b6595 100644 --- a/lib/Target/PowerPC/PPCInstrFormats.td +++ b/lib/Target/PowerPC/PPCInstrFormats.td @@ -800,10 +800,9 @@ class DCB_Form xo, bits<5> immfield, dag OOL, dag IOL, string asmstr, // DSS_Form - Form X instruction, used for altivec dss* instructions. -class DSS_Form xo, dag OOL, dag IOL, string asmstr, +class DSS_Form T, bits<10> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list pattern> : I<31, OOL, IOL, asmstr, itin> { - bits<1> T; bits<2> STRM; bits<5> A; bits<5> B; diff --git a/test/MC/Disassembler/PowerPC/ppc64-encoding-ext.txt b/test/MC/Disassembler/PowerPC/ppc64-encoding-ext.txt index 2998e8d1ab7..b55ebce81a2 100644 --- a/test/MC/Disassembler/PowerPC/ppc64-encoding-ext.txt +++ b/test/MC/Disassembler/PowerPC/ppc64-encoding-ext.txt @@ -2255,3 +2255,16 @@ 0x4c 0x00 0x00 0x4e # CHECK: rfmci 0x4c 0x00 0x00 0x4c + +# CHECK: dss 3 +0x7c 0x60 0x06 0x6c +# CHECK: dssall +0x7e 0x00 0x06 0x6c +# CHECK: dst 12, 11, 3 +0x7c 0x6c 0x5a 0xac +# CHECK: dstt 12, 11, 3 +0x7e 0x6c 0x5a 0xac +# CHECK: dstst 12, 11, 3 +0x7c 0x6c 0x5a 0xec +# CHECK: dststt 12, 11, 3 +0x7e 0x6c 0x5a 0xec diff --git a/test/MC/PowerPC/ppc64-encoding-ext.s b/test/MC/PowerPC/ppc64-encoding-ext.s index 258b594698d..2e9316f848f 100644 --- a/test/MC/PowerPC/ppc64-encoding-ext.s +++ b/test/MC/PowerPC/ppc64-encoding-ext.s @@ -3593,3 +3593,23 @@ # CHECK-BE: rfmci # encoding: [0x4c,0x00,0x00,0x4c] # CHECK-LE: rfmci # encoding: [0x4c,0x00,0x00,0x4c] rfmci + +# Altivec Data Stream instruction: +# CHECK-BE: dss 3 # encoding: [0x7c,0x60,0x06,0x6c] +# CHECK-LE: dss 3 # encoding: [0x6c,0x06,0x60,0x7c] + dss 3 +# CHECK-BE: dssall # encoding: [0x7e,0x00,0x06,0x6c] +# CHECK-LE: dssall # encoding: [0x6c,0x06,0x00,0x7e] + dssall +# CHECK-BE: dst 12, 11, 3 # encoding: [0x7c,0x6c,0x5a,0xac] +# CHECK-LE: dst 12, 11, 3 # encoding: [0xac,0x5a,0x6c,0x7c] + dst %r12, %r11, 3 +# CHECK-BE: dstt 12, 11, 3 # encoding: [0x7e,0x6c,0x5a,0xac] +# CHECK-LE: dstt 12, 11, 3 # encoding: [0xac,0x5a,0x6c,0x7e] + dstt %r12, %r11, 3 +# CHECK-BE: dstst 12, 11, 3 # encoding: [0x7c,0x6c,0x5a,0xec] +# CHECK-LE: dstst 12, 11, 3 # encoding: [0xec,0x5a,0x6c,0x7c] + dstst %r12, %r11, 3 +# CHECK-BE: dststt 12, 11, 3 # encoding: [0x7e,0x6c,0x5a,0xec] +# CHECK-LE: dststt 12, 11, 3 # encoding: [0xec,0x5a,0x6c,0x7e] + dststt %r12, %r11, 3