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Improve X86 subtarget support for Windows and AMD.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25747 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jeff Cohen 2006-01-28 18:09:06 +00:00
parent c52ad4f04e
commit 41adb0d679
1 changed files with 77 additions and 38 deletions
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115
lib/Target/X86/X86Subtarget.cpp
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@ -25,20 +25,34 @@ namespace {
/// GetCpuIDAndInfo - Execute the specified cpuid and return the 4 values in the
/// specified arguments. If we can't run cpuid on the host, return true.
static bool GetCpuIDAndInfo(unsigned value, unsigned *EAX, unsigned *EBX,
unsigned *ECX, unsigned *EDX) {
static bool GetCpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX,
unsigned *rECX, unsigned *rEDX) {
#if defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
#if defined(__GNUC__)
asm ("pushl\t%%ebx\n\t"
"cpuid\n\t"
"movl\t%%ebx, %%esi\n\t"
"popl\t%%ebx"
: "=a" (*EAX),
"=S" (*EBX),
"=c" (*ECX),
"=d" (*EDX)
: "=a" (*rEAX),
"=S" (*rEBX),
"=c" (*rECX),
"=d" (*rEDX)
: "a" (value));
return false;
#elif defined(_MSC_VER)
__asm {
mov eax,value
cpuid
mov esi,rEAX
mov dword ptr [esi],eax
mov esi,rEBX
mov dword ptr [esi],ebx
mov esi,rECX
mov dword ptr [esi],ecx
mov esi,rEDX
mov dword ptr [esi],edx
}
return false;
#endif
#endif
return true;
@ -53,42 +67,61 @@ static const char *GetCurrentX86CPU() {
GetCpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
bool Em64T = EDX & (1 << 29);
switch (Family) {
case 3:
return "i386";
case 4:
return "i486";
case 5:
switch (Model) {
case 4: return "pentium-mmx";
default: return "pentium";
}
case 6:
switch (Model) {
case 1: return "pentiumpro";
unsigned text[12];
GetCpuIDAndInfo(0x80000002, text+0, text+1, text+2, text+3);
GetCpuIDAndInfo(0x80000003, text+4, text+5, text+6, text+7);
GetCpuIDAndInfo(0x80000004, text+8, text+9, text+10, text+11);
char *t = reinterpret_cast<char *>(&text[0]);
if (memcmp(t, "Intel", 5) == 0) {
switch (Family) {
case 3:
case 5:
case 6: return "pentium2";
case 7:
case 8:
case 10:
case 11: return "pentium3";
case 9:
case 13: return "pentium-m";
case 14: return "yonah";
default: return "i686";
}
case 15: {
switch (Model) {
case 3:
return "i386";
case 4:
return (Em64T) ? "nocona" : "prescott";
default:
return (Em64T) ? "x86-64" : "pentium4";
return "i486";
case 5:
switch (Model) {
case 4: return "pentium-mmx";
default: return "pentium";
}
case 6:
switch (Model) {
case 1: return "pentiumpro";
case 3:
case 5:
case 6: return "pentium2";
case 7:
case 8:
case 10:
case 11: return "pentium3";
case 9:
case 13: return "pentium-m";
case 14: return "yonah";
default: return "i686";
}
case 15: {
switch (Model) {
case 3:
case 4:
return (Em64T) ? "nocona" : "prescott";
default:
return (Em64T) ? "x86-64" : "pentium4";
}
}
default:
return "generic";
}
default:
} else if (memcmp(t, "AMD", 3) == 0) {
// FIXME: fill in remaining family/model combinations
switch (Family) {
case 15:
return (Em64T) ? "athlon64" : "athlon";
default:
return "generic";
}
} else {
return "generic";
}
}
@ -106,6 +139,12 @@ X86Subtarget::X86Subtarget(const Module &M, const std::string &FS) {
// Parse features string.
ParseSubtargetFeatures(FS, CPU);
// FIXME: Just because the CPU supports 64-bit operation doesn't mean it isn't
// currently running a 32-bit operating system. This must be taken into account.
// This hack will do for now, though obviously it breaks cross-compilation.
if (sizeof(void *) == 4)
Is64Bit = false;
// Default to ELF unless otherwise specified.
TargetType = isELF;