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Define SPARC code models.

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Currently, only abs32 and pic32 are implemented. Add a test case for
abs32 with 64-bit code. 64-bit PIC code is currently broken.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179463 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen 2013-04-13 19:02:23 +00:00
parent 41b585ca0e
commit 41d59c6130
3 changed files with 55 additions and 4 deletions
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30
lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp
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@ -50,14 +50,42 @@ static MCSubtargetInfo *createSparcMCSubtargetInfo(StringRef TT, StringRef CPU,
return X;
}
// Code models. Some only make sense for 64-bit code.
//
// SunCC Reloc CodeModel Constraints
// abs32 Static Small text+data+bss linked below 2^32 bytes
// abs44 Static Medium text+data+bss linked below 2^44 bytes
// abs64 Static Large text smaller than 2^31 bytes
// pic13 PIC_ Small GOT < 2^13 bytes
// pic32 PIC_ Medium GOT < 2^32 bytes
//
// All code models require that the text segment is smaller than 2GB.
static MCCodeGenInfo *createSparcMCCodeGenInfo(StringRef TT, Reloc::Model RM,
CodeModel::Model CM,
CodeGenOpt::Level OL) {
MCCodeGenInfo *X = new MCCodeGenInfo();
// The default 32-bit code model is abs32/pic32.
if (CM == CodeModel::Default)
CM = RM == Reloc::PIC_ ? CodeModel::Medium : CodeModel::Small;
X->InitMCCodeGenInfo(RM, CM, OL);
return X;
}
static MCCodeGenInfo *createSparcV9MCCodeGenInfo(StringRef TT, Reloc::Model RM,
CodeModel::Model CM,
CodeGenOpt::Level OL) {
MCCodeGenInfo *X = new MCCodeGenInfo();
// The default 64-bit code model is abs44/pic32.
if (CM == CodeModel::Default)
CM = CodeModel::Medium;
X->InitMCCodeGenInfo(RM, CM, OL);
return X;
}
extern "C" void LLVMInitializeSparcTargetMC() {
// Register the MC asm info.
RegisterMCAsmInfo<SparcELFMCAsmInfo> X(TheSparcTarget);
@ -67,7 +95,7 @@ extern "C" void LLVMInitializeSparcTargetMC() {
TargetRegistry::RegisterMCCodeGenInfo(TheSparcTarget,
createSparcMCCodeGenInfo);
TargetRegistry::RegisterMCCodeGenInfo(TheSparcV9Target,
createSparcMCCodeGenInfo);
createSparcV9MCCodeGenInfo);
// Register the MC instruction info.
TargetRegistry::RegisterMCInstrInfo(TheSparcTarget, createSparcMCInstrInfo);

6
lib/Target/Sparc/SparcISelLowering.cpp
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@ -1167,9 +1167,9 @@ SparcTargetLowering::SparcTargetLowering(TargetMachine &TM)
setTruncStoreAction(MVT::f64, MVT::f32, Expand);
// Custom legalize GlobalAddress nodes into LO/HI parts.
setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
setOperationAction(ISD::ConstantPool , MVT::i32, Custom);
setOperationAction(ISD::GlobalAddress, getPointerTy(), Custom);
setOperationAction(ISD::GlobalTLSAddress, getPointerTy(), Custom);
setOperationAction(ISD::ConstantPool, getPointerTy(), Custom);
// Sparc doesn't have sext_inreg, replace them with shl/sra
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);

23
test/CodeGen/SPARC/globals.ll Normal file
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@ -0,0 +1,23 @@
; RUN: llc < %s -march=sparc -relocation-model=static -code-model=small | FileCheck --check-prefix=abs32 %s
; RUN: llc < %s -march=sparcv9 -relocation-model=static -code-model=small | FileCheck --check-prefix=abs32 %s
; RUN: llc < %s -march=sparc -relocation-model=pic -code-model=medium | FileCheck --check-prefix=v8pic32 %s
@G = external global i8
define zeroext i8 @loadG() {
%tmp = load i8* @G
ret i8 %tmp
}
; abs32: loadG
; abs32: sethi %hi(G), %[[R:[gilo][0-7]]]
; abs32: ldub [%[[R]]+%lo(G)], %i0
; abs32: jmp %i7+8
; v8pic32: loadG
; v8pic32: _GLOBAL_OFFSET_TABLE_
; v8pic32: sethi %hi(G), %[[R1:[gilo][0-7]]]
; v8pic32: add %[[R1]], %lo(G), %[[Goffs:[gilo][0-7]]]
; v8pic32: ld [%[[GOT:[gilo][0-7]]]+%[[Goffs]]], %[[Gaddr:[gilo][0-7]]]
; v8pic32: ldub [%[[Gaddr]]], %i0
; v8pic32: jmp %i7+8