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Don't cache the instruction and register info from the TargetMachine, because
the internals of TargetMachine could change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183493 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
ed8b5b55a4
commit
41e632d9e1
@ -37,7 +37,7 @@ static cl::opt<bool> NeverUseSaveRestore(
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Mips16InstrInfo::Mips16InstrInfo(MipsTargetMachine &tm)
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Mips16InstrInfo::Mips16InstrInfo(MipsTargetMachine &tm)
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: MipsInstrInfo(tm, Mips::BimmX16),
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: MipsInstrInfo(tm, Mips::BimmX16),
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RI(*tm.getSubtargetImpl(), *this) {}
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RI(*tm.getSubtargetImpl()) {}
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const MipsRegisterInfo &Mips16InstrInfo::getRegisterInfo() const {
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const MipsRegisterInfo &Mips16InstrInfo::getRegisterInfo() const {
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return RI;
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return RI;
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@ -41,9 +41,8 @@
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using namespace llvm;
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using namespace llvm;
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Mips16RegisterInfo::Mips16RegisterInfo(const MipsSubtarget &ST,
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Mips16RegisterInfo::Mips16RegisterInfo(const MipsSubtarget &ST)
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const Mips16InstrInfo &I)
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: MipsRegisterInfo(ST) {}
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: MipsRegisterInfo(ST), TII(I) {}
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bool Mips16RegisterInfo::requiresRegisterScavenging
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bool Mips16RegisterInfo::requiresRegisterScavenging
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(const MachineFunction &MF) const {
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(const MachineFunction &MF) const {
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@ -66,6 +65,7 @@ bool Mips16RegisterInfo::saveScavengerRegister
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const TargetRegisterClass *RC,
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const TargetRegisterClass *RC,
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unsigned Reg) const {
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unsigned Reg) const {
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DebugLoc DL;
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DebugLoc DL;
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const TargetInstrInfo &TII = *MBB.getParent()->getTarget().getInstrInfo();
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TII.copyPhysReg(MBB, I, DL, Mips::T0, Reg, true);
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TII.copyPhysReg(MBB, I, DL, Mips::T0, Reg, true);
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TII.copyPhysReg(MBB, UseMI, DL, Reg, Mips::T0, true);
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TII.copyPhysReg(MBB, UseMI, DL, Reg, Mips::T0, true);
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return true;
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return true;
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@ -139,6 +139,9 @@ void Mips16RegisterInfo::eliminateFI(MachineBasicBlock::iterator II,
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MachineBasicBlock &MBB = *MI.getParent();
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MachineBasicBlock &MBB = *MI.getParent();
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DebugLoc DL = II->getDebugLoc();
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DebugLoc DL = II->getDebugLoc();
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unsigned NewImm;
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unsigned NewImm;
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const Mips16InstrInfo &TII =
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*static_cast<const Mips16InstrInfo*>(
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MBB.getParent()->getTarget().getInstrInfo());
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FrameReg = TII.loadImmediate(FrameReg, Offset, MBB, II, DL, NewImm);
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FrameReg = TII.loadImmediate(FrameReg, Offset, MBB, II, DL, NewImm);
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Offset = SignExtend64<16>(NewImm);
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Offset = SignExtend64<16>(NewImm);
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IsKill = true;
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IsKill = true;
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@ -20,10 +20,8 @@ namespace llvm {
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class Mips16InstrInfo;
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class Mips16InstrInfo;
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class Mips16RegisterInfo : public MipsRegisterInfo {
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class Mips16RegisterInfo : public MipsRegisterInfo {
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const Mips16InstrInfo &TII;
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public:
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public:
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Mips16RegisterInfo(const MipsSubtarget &Subtarget,
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Mips16RegisterInfo(const MipsSubtarget &Subtarget);
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const Mips16InstrInfo &TII);
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bool requiresRegisterScavenging(const MachineFunction &MF) const;
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bool requiresRegisterScavenging(const MachineFunction &MF) const;
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@ -65,8 +65,7 @@ class MipsCodeEmitter : public MachineFunctionPass {
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public:
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public:
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MipsCodeEmitter(TargetMachine &tm, JITCodeEmitter &mce)
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MipsCodeEmitter(TargetMachine &tm, JITCodeEmitter &mce)
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: MachineFunctionPass(ID), JTI(0),
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: MachineFunctionPass(ID), JTI(0), II(0), TD(0),
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II((const MipsInstrInfo *) tm.getInstrInfo()), TD(tm.getDataLayout()),
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TM(tm), MCE(mce), MCPEs(0), MJTEs(0),
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TM(tm), MCE(mce), MCPEs(0), MJTEs(0),
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IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
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IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
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@ -50,7 +50,6 @@ namespace {
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static char ID;
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static char ID;
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MipsConstantIslands(TargetMachine &tm)
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MipsConstantIslands(TargetMachine &tm)
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: MachineFunctionPass(ID), TM(tm),
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: MachineFunctionPass(ID), TM(tm),
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TII(static_cast<const MipsInstrInfo*>(tm.getInstrInfo())),
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IsPIC(TM.getRelocationModel() == Reloc::PIC_),
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IsPIC(TM.getRelocationModel() == Reloc::PIC_),
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ABI(TM.getSubtarget<MipsSubtarget>().getTargetABI()) {}
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ABI(TM.getSubtarget<MipsSubtarget>().getTargetABI()) {}
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@ -61,13 +60,9 @@ namespace {
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bool runOnMachineFunction(MachineFunction &F);
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bool runOnMachineFunction(MachineFunction &F);
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private:
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private:
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const TargetMachine &TM;
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const TargetMachine &TM;
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const MipsInstrInfo *TII;
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bool IsPIC;
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bool IsPIC;
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unsigned ABI;
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unsigned ABI;
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};
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};
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char MipsConstantIslands::ID = 0;
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char MipsConstantIslands::ID = 0;
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@ -177,7 +177,7 @@ namespace {
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class Filler : public MachineFunctionPass {
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class Filler : public MachineFunctionPass {
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public:
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public:
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Filler(TargetMachine &tm)
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Filler(TargetMachine &tm)
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: MachineFunctionPass(ID), TM(tm), TII(tm.getInstrInfo()) { }
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: MachineFunctionPass(ID), TM(tm) { }
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virtual const char *getPassName() const {
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virtual const char *getPassName() const {
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return "Mips Delay Slot Filler";
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return "Mips Delay Slot Filler";
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@ -243,7 +243,6 @@ namespace {
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bool terminateSearch(const MachineInstr &Candidate) const;
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bool terminateSearch(const MachineInstr &Candidate) const;
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TargetMachine &TM;
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TargetMachine &TM;
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const TargetInstrInfo *TII;
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static char ID;
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static char ID;
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};
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};
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@ -514,6 +513,8 @@ bool Filler::runOnMachineBasicBlock(MachineBasicBlock &MBB) {
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}
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}
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// Bundle the NOP to the instruction with the delay slot.
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// Bundle the NOP to the instruction with the delay slot.
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const MipsInstrInfo *TII =
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static_cast<const MipsInstrInfo*>(TM.getInstrInfo());
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BuildMI(MBB, llvm::next(I), I->getDebugLoc(), TII->get(Mips::NOP));
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BuildMI(MBB, llvm::next(I), I->getDebugLoc(), TII->get(Mips::NOP));
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MIBundleBuilder(MBB, I, llvm::next(llvm::next(I)));
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MIBundleBuilder(MBB, I, llvm::next(llvm::next(I)));
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}
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}
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@ -65,7 +65,6 @@ namespace {
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static char ID;
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static char ID;
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MipsLongBranch(TargetMachine &tm)
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MipsLongBranch(TargetMachine &tm)
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: MachineFunctionPass(ID), TM(tm),
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: MachineFunctionPass(ID), TM(tm),
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TII(static_cast<const MipsInstrInfo*>(tm.getInstrInfo())),
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IsPIC(TM.getRelocationModel() == Reloc::PIC_),
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IsPIC(TM.getRelocationModel() == Reloc::PIC_),
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ABI(TM.getSubtarget<MipsSubtarget>().getTargetABI()),
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ABI(TM.getSubtarget<MipsSubtarget>().getTargetABI()),
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LongBranchSeqSize(!IsPIC ? 2 : (ABI == MipsSubtarget::N64 ? 13 : 9)) {}
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LongBranchSeqSize(!IsPIC ? 2 : (ABI == MipsSubtarget::N64 ? 13 : 9)) {}
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@ -85,7 +84,6 @@ namespace {
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void expandToLongBranch(MBBInfo &Info);
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void expandToLongBranch(MBBInfo &Info);
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const TargetMachine &TM;
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const TargetMachine &TM;
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const MipsInstrInfo *TII;
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MachineFunction *MF;
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MachineFunction *MF;
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SmallVector<MBBInfo, 16> MBBInfos;
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SmallVector<MBBInfo, 16> MBBInfos;
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bool IsPIC;
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bool IsPIC;
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@ -172,6 +170,8 @@ void MipsLongBranch::initMBBInfo() {
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MBBInfos.clear();
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MBBInfos.clear();
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MBBInfos.resize(MF->size());
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MBBInfos.resize(MF->size());
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const MipsInstrInfo *TII =
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static_cast<const MipsInstrInfo*>(TM.getInstrInfo());
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for (unsigned I = 0, E = MBBInfos.size(); I < E; ++I) {
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for (unsigned I = 0, E = MBBInfos.size(); I < E; ++I) {
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MachineBasicBlock *MBB = MF->getBlockNumbered(I);
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MachineBasicBlock *MBB = MF->getBlockNumbered(I);
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@ -217,6 +217,8 @@ int64_t MipsLongBranch::computeOffset(const MachineInstr *Br) {
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// MachineBasicBlock operand MBBOpnd.
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// MachineBasicBlock operand MBBOpnd.
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void MipsLongBranch::replaceBranch(MachineBasicBlock &MBB, Iter Br,
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void MipsLongBranch::replaceBranch(MachineBasicBlock &MBB, Iter Br,
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DebugLoc DL, MachineBasicBlock *MBBOpnd) {
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DebugLoc DL, MachineBasicBlock *MBBOpnd) {
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const MipsInstrInfo *TII =
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static_cast<const MipsInstrInfo*>(TM.getInstrInfo());
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unsigned NewOpc = TII->getOppositeBranchOpc(Br->getOpcode());
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unsigned NewOpc = TII->getOppositeBranchOpc(Br->getOpcode());
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const MCInstrDesc &NewDesc = TII->get(NewOpc);
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const MCInstrDesc &NewDesc = TII->get(NewOpc);
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@ -247,6 +249,9 @@ void MipsLongBranch::expandToLongBranch(MBBInfo &I) {
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MachineFunction::iterator FallThroughMBB = ++MachineFunction::iterator(MBB);
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MachineFunction::iterator FallThroughMBB = ++MachineFunction::iterator(MBB);
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MachineBasicBlock *LongBrMBB = MF->CreateMachineBasicBlock(BB);
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MachineBasicBlock *LongBrMBB = MF->CreateMachineBasicBlock(BB);
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const MipsInstrInfo *TII =
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static_cast<const MipsInstrInfo*>(TM.getInstrInfo());
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MF->insert(FallThroughMBB, LongBrMBB);
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MF->insert(FallThroughMBB, LongBrMBB);
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MBB->removeSuccessor(TgtMBB);
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MBB->removeSuccessor(TgtMBB);
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MBB->addSuccessor(LongBrMBB);
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MBB->addSuccessor(LongBrMBB);
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@ -399,6 +404,9 @@ static void emitGPDisp(MachineFunction &F, const MipsInstrInfo *TII) {
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}
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}
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bool MipsLongBranch::runOnMachineFunction(MachineFunction &F) {
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bool MipsLongBranch::runOnMachineFunction(MachineFunction &F) {
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const MipsInstrInfo *TII =
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static_cast<const MipsInstrInfo*>(TM.getInstrInfo());
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if (TM.getSubtarget<MipsSubtarget>().inMips16Mode())
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if (TM.getSubtarget<MipsSubtarget>().inMips16Mode())
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return false;
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return false;
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if ((TM.getRelocationModel() == Reloc::PIC_) &&
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if ((TM.getRelocationModel() == Reloc::PIC_) &&
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@ -49,16 +49,12 @@ private:
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unsigned Src, unsigned RegSize);
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unsigned Src, unsigned RegSize);
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MachineFunction &MF;
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MachineFunction &MF;
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const MipsSEInstrInfo &TII;
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const MipsRegisterInfo &RegInfo;
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MachineRegisterInfo &MRI;
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MachineRegisterInfo &MRI;
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};
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};
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}
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}
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ExpandPseudo::ExpandPseudo(MachineFunction &MF_)
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ExpandPseudo::ExpandPseudo(MachineFunction &MF_)
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: MF(MF_),
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: MF(MF_), MRI(MF.getRegInfo()) {}
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TII(*static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo())),
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RegInfo(TII.getRegisterInfo()), MRI(MF.getRegInfo()) {}
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bool ExpandPseudo::expand() {
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bool ExpandPseudo::expand() {
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bool Expanded = false;
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bool Expanded = false;
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@ -119,6 +115,11 @@ void ExpandPseudo::expandLoadCCond(MachineBasicBlock &MBB, Iter I) {
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assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
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assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
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const MipsSEInstrInfo &TII =
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*static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo());
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const MipsRegisterInfo &RegInfo =
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*static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo());
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const TargetRegisterClass *RC = RegInfo.intRegClass(4);
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const TargetRegisterClass *RC = RegInfo.intRegClass(4);
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unsigned VR = MRI.createVirtualRegister(RC);
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unsigned VR = MRI.createVirtualRegister(RC);
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unsigned Dst = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
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unsigned Dst = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
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@ -134,6 +135,11 @@ void ExpandPseudo::expandStoreCCond(MachineBasicBlock &MBB, Iter I) {
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assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
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assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
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const MipsSEInstrInfo &TII =
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*static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo());
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const MipsRegisterInfo &RegInfo =
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*static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo());
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const TargetRegisterClass *RC = RegInfo.intRegClass(4);
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const TargetRegisterClass *RC = RegInfo.intRegClass(4);
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unsigned VR = MRI.createVirtualRegister(RC);
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unsigned VR = MRI.createVirtualRegister(RC);
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unsigned Src = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
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unsigned Src = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
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@ -152,6 +158,11 @@ void ExpandPseudo::expandLoadACC(MachineBasicBlock &MBB, Iter I,
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assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
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assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
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const MipsSEInstrInfo &TII =
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*static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo());
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const MipsRegisterInfo &RegInfo =
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*static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo());
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const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize);
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const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize);
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unsigned VR0 = MRI.createVirtualRegister(RC);
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unsigned VR0 = MRI.createVirtualRegister(RC);
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unsigned VR1 = MRI.createVirtualRegister(RC);
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unsigned VR1 = MRI.createVirtualRegister(RC);
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@ -176,6 +187,11 @@ void ExpandPseudo::expandStoreACC(MachineBasicBlock &MBB, Iter I,
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assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
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assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
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const MipsSEInstrInfo &TII =
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*static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo());
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const MipsRegisterInfo &RegInfo =
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*static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo());
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const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize);
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const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize);
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unsigned VR0 = MRI.createVirtualRegister(RC);
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unsigned VR0 = MRI.createVirtualRegister(RC);
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unsigned VR1 = MRI.createVirtualRegister(RC);
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unsigned VR1 = MRI.createVirtualRegister(RC);
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@ -210,6 +226,11 @@ bool ExpandPseudo::expandCopyACC(MachineBasicBlock &MBB, Iter I, unsigned Dst,
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// copy $vr1, src_hi
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// copy $vr1, src_hi
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// copy dst_hi, $vr1
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// copy dst_hi, $vr1
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const MipsSEInstrInfo &TII =
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*static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo());
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const MipsRegisterInfo &RegInfo =
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*static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo());
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const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize);
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const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize);
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unsigned VR0 = MRI.createVirtualRegister(RC);
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unsigned VR0 = MRI.createVirtualRegister(RC);
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unsigned VR1 = MRI.createVirtualRegister(RC);
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unsigned VR1 = MRI.createVirtualRegister(RC);
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@ -244,10 +265,12 @@ void MipsSEFrameLowering::emitPrologue(MachineFunction &MF) const {
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MachineBasicBlock &MBB = MF.front();
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MachineBasicBlock &MBB = MF.front();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
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MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
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const MipsRegisterInfo *RegInfo =
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static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo());
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const MipsSEInstrInfo &TII =
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const MipsSEInstrInfo &TII =
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*static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo());
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*static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo());
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const MipsRegisterInfo &RegInfo =
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*static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo());
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MachineBasicBlock::iterator MBBI = MBB.begin();
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MachineBasicBlock::iterator MBBI = MBB.begin();
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DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
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DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
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unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP;
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unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP;
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@ -298,9 +321,9 @@ void MipsSEFrameLowering::emitPrologue(MachineFunction &MF) const {
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// one for each of the paired single precision registers.
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// one for each of the paired single precision registers.
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if (Mips::AFGR64RegClass.contains(Reg)) {
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if (Mips::AFGR64RegClass.contains(Reg)) {
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unsigned Reg0 =
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unsigned Reg0 =
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MRI.getDwarfRegNum(RegInfo->getSubReg(Reg, Mips::sub_fpeven), true);
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MRI.getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_fpeven), true);
|
||||||
unsigned Reg1 =
|
unsigned Reg1 =
|
||||||
MRI.getDwarfRegNum(RegInfo->getSubReg(Reg, Mips::sub_fpodd), true);
|
MRI.getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_fpodd), true);
|
||||||
|
|
||||||
if (!STI.isLittle())
|
if (!STI.isLittle())
|
||||||
std::swap(Reg0, Reg1);
|
std::swap(Reg0, Reg1);
|
||||||
@ -326,7 +349,7 @@ void MipsSEFrameLowering::emitPrologue(MachineFunction &MF) const {
|
|||||||
if (!MBB.isLiveIn(ehDataReg(I)))
|
if (!MBB.isLiveIn(ehDataReg(I)))
|
||||||
MBB.addLiveIn(ehDataReg(I));
|
MBB.addLiveIn(ehDataReg(I));
|
||||||
TII.storeRegToStackSlot(MBB, MBBI, ehDataReg(I), false,
|
TII.storeRegToStackSlot(MBB, MBBI, ehDataReg(I), false,
|
||||||
MipsFI->getEhDataRegFI(I), RC, RegInfo);
|
MipsFI->getEhDataRegFI(I), RC, &RegInfo);
|
||||||
}
|
}
|
||||||
|
|
||||||
// Emit .cfi_offset directives for eh data registers.
|
// Emit .cfi_offset directives for eh data registers.
|
||||||
@ -359,10 +382,12 @@ void MipsSEFrameLowering::emitEpilogue(MachineFunction &MF,
|
|||||||
MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
|
MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
|
||||||
MachineFrameInfo *MFI = MF.getFrameInfo();
|
MachineFrameInfo *MFI = MF.getFrameInfo();
|
||||||
MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
|
MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
|
||||||
const MipsRegisterInfo *RegInfo =
|
|
||||||
static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo());
|
|
||||||
const MipsSEInstrInfo &TII =
|
const MipsSEInstrInfo &TII =
|
||||||
*static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo());
|
*static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo());
|
||||||
|
const MipsRegisterInfo &RegInfo =
|
||||||
|
*static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo());
|
||||||
|
|
||||||
DebugLoc dl = MBBI->getDebugLoc();
|
DebugLoc dl = MBBI->getDebugLoc();
|
||||||
unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP;
|
unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP;
|
||||||
unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP;
|
unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP;
|
||||||
@ -393,7 +418,7 @@ void MipsSEFrameLowering::emitEpilogue(MachineFunction &MF,
|
|||||||
// Insert instructions that restore eh data registers.
|
// Insert instructions that restore eh data registers.
|
||||||
for (int J = 0; J < 4; ++J) {
|
for (int J = 0; J < 4; ++J) {
|
||||||
TII.loadRegFromStackSlot(MBB, I, ehDataReg(J), MipsFI->getEhDataRegFI(J),
|
TII.loadRegFromStackSlot(MBB, I, ehDataReg(J), MipsFI->getEhDataRegFI(J),
|
||||||
RC, RegInfo);
|
RC, &RegInfo);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -32,7 +32,7 @@ static cl::opt<bool> NoDPLoadStore("mno-ldc1-sdc1", cl::init(false),
|
|||||||
MipsSEInstrInfo::MipsSEInstrInfo(MipsTargetMachine &tm)
|
MipsSEInstrInfo::MipsSEInstrInfo(MipsTargetMachine &tm)
|
||||||
: MipsInstrInfo(tm,
|
: MipsInstrInfo(tm,
|
||||||
tm.getRelocationModel() == Reloc::PIC_ ? Mips::B : Mips::J),
|
tm.getRelocationModel() == Reloc::PIC_ ? Mips::B : Mips::J),
|
||||||
RI(*tm.getSubtargetImpl(), *this),
|
RI(*tm.getSubtargetImpl()),
|
||||||
IsN64(tm.getSubtarget<MipsSubtarget>().isABI_N64()) {}
|
IsN64(tm.getSubtarget<MipsSubtarget>().isABI_N64()) {}
|
||||||
|
|
||||||
const MipsRegisterInfo &MipsSEInstrInfo::getRegisterInfo() const {
|
const MipsRegisterInfo &MipsSEInstrInfo::getRegisterInfo() const {
|
||||||
|
@ -40,9 +40,8 @@
|
|||||||
|
|
||||||
using namespace llvm;
|
using namespace llvm;
|
||||||
|
|
||||||
MipsSERegisterInfo::MipsSERegisterInfo(const MipsSubtarget &ST,
|
MipsSERegisterInfo::MipsSERegisterInfo(const MipsSubtarget &ST)
|
||||||
const MipsSEInstrInfo &I)
|
: MipsRegisterInfo(ST) {}
|
||||||
: MipsRegisterInfo(ST), TII(I) {}
|
|
||||||
|
|
||||||
bool MipsSERegisterInfo::
|
bool MipsSERegisterInfo::
|
||||||
requiresRegisterScavenging(const MachineFunction &MF) const {
|
requiresRegisterScavenging(const MachineFunction &MF) const {
|
||||||
@ -119,7 +118,9 @@ void MipsSERegisterInfo::eliminateFI(MachineBasicBlock::iterator II,
|
|||||||
DebugLoc DL = II->getDebugLoc();
|
DebugLoc DL = II->getDebugLoc();
|
||||||
unsigned ADDu = Subtarget.isABI_N64() ? Mips::DADDu : Mips::ADDu;
|
unsigned ADDu = Subtarget.isABI_N64() ? Mips::DADDu : Mips::ADDu;
|
||||||
unsigned NewImm;
|
unsigned NewImm;
|
||||||
|
const MipsSEInstrInfo &TII =
|
||||||
|
*static_cast<const MipsSEInstrInfo*>(
|
||||||
|
MBB.getParent()->getTarget().getInstrInfo());
|
||||||
unsigned Reg = TII.loadImmediate(Offset, MBB, II, DL, &NewImm);
|
unsigned Reg = TII.loadImmediate(Offset, MBB, II, DL, &NewImm);
|
||||||
BuildMI(MBB, II, DL, TII.get(ADDu), Reg).addReg(FrameReg)
|
BuildMI(MBB, II, DL, TII.get(ADDu), Reg).addReg(FrameReg)
|
||||||
.addReg(Reg, RegState::Kill);
|
.addReg(Reg, RegState::Kill);
|
||||||
|
@ -21,11 +21,8 @@ namespace llvm {
|
|||||||
class MipsSEInstrInfo;
|
class MipsSEInstrInfo;
|
||||||
|
|
||||||
class MipsSERegisterInfo : public MipsRegisterInfo {
|
class MipsSERegisterInfo : public MipsRegisterInfo {
|
||||||
const MipsSEInstrInfo &TII;
|
|
||||||
|
|
||||||
public:
|
public:
|
||||||
MipsSERegisterInfo(const MipsSubtarget &Subtarget,
|
MipsSERegisterInfo(const MipsSubtarget &Subtarget);
|
||||||
const MipsSEInstrInfo &TII);
|
|
||||||
|
|
||||||
bool requiresRegisterScavenging(const MachineFunction &MF) const;
|
bool requiresRegisterScavenging(const MachineFunction &MF) const;
|
||||||
|
|
||||||
|
Loading…
Reference in New Issue
Block a user