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- Make lowering of "add with overflow" customizable by back-ends.
- Mark "add with overflow" as having a custom lowering for X86. Give it a null lowering representation for now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59971 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -4172,22 +4172,34 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
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case ISD::SADDO:
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case ISD::UADDO: {
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SDValue LHS = LegalizeOp(Node->getOperand(0));
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SDValue RHS = LegalizeOp(Node->getOperand(1));
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MVT VT = Node->getValueType(0);
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switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
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default: assert(0 && "This action not supported for this op yet!");
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case TargetLowering::Custom:
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Result = TLI.LowerOperation(Op, DAG);
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if (Result.getNode()) break;
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// FALLTHROUGH
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case TargetLowering::Legal: {
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SDValue LHS = LegalizeOp(Node->getOperand(0));
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SDValue RHS = LegalizeOp(Node->getOperand(1));
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SDValue Sum = DAG.getNode(ISD::ADD, LHS.getValueType(), LHS, RHS);
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MVT OType = SDValue(Node, 1).getValueType();
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SDValue Cmp = DAG.getSetCC(OType, Sum, LHS,
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(Node->getOpcode() == ISD::SADDO) ?
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ISD::SETLT : ISD::SETULT);
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SDValue Sum = DAG.getNode(ISD::ADD, LHS.getValueType(), LHS, RHS);
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MVT OType = Node->getValueType(1);
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SDValue Cmp = DAG.getSetCC(OType, Sum, LHS,
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(Node->getOpcode() == ISD::SADDO) ?
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ISD::SETLT : ISD::SETULT);
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MVT ValueVTs[] = { LHS.getValueType(), OType };
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SDValue Ops[] = { Sum, Cmp };
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MVT ValueVTs[] = { LHS.getValueType(), OType };
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SDValue Ops[] = { Sum, Cmp };
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Result = DAG.getMergeValues(DAG.getVTList(&ValueVTs[0], 2), &Ops[0], 2);
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SDNode *RNode = Result.getNode();
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DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), SDValue(RNode, 0));
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DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), SDValue(RNode, 1));
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break;
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}
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}
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Result = DAG.getMergeValues(DAG.getVTList(&ValueVTs[0], 2), &Ops[0], 2);
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SDNode *RNode = Result.getNode();
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DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), SDValue(RNode, 0));
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DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), SDValue(RNode, 1));
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break;
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}
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}
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@ -4096,9 +4096,8 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
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case Intrinsic::sadd_with_overflow: {
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SDValue Op1 = getValue(I.getOperand(1));
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SDValue Op2 = getValue(I.getOperand(2));
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MVT Ty = Op1.getValueType();
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MVT ValueVTs[] = { Ty, MVT::i1 };
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MVT ValueVTs[] = { Op1.getValueType(), MVT::i1 };
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SDValue Ops[] = { Op1, Op2 };
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SDValue Result =
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@ -780,6 +780,12 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
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// We want to custom lower some of our intrinsics.
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setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
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// Add with overflow operations are custom lowered.
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setOperationAction(ISD::SADDO, MVT::i32, Custom);
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setOperationAction(ISD::SADDO, MVT::i64, Custom);
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setOperationAction(ISD::UADDO, MVT::i32, Custom);
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setOperationAction(ISD::UADDO, MVT::i64, Custom);
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// We have target-specific dag combine patterns for the following nodes:
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setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
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setTargetDAGCombine(ISD::BUILD_VECTOR);
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@ -6142,6 +6148,11 @@ SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
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return Op;
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}
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SDValue X86TargetLowering::LowerXADDO(SDValue Op, SelectionDAG &DAG,
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ISD::NodeType NTy) {
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return SDValue();
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}
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SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) {
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MVT T = Op.getValueType();
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unsigned Reg = 0;
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@ -6321,6 +6332,8 @@ SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
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case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
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case ISD::CTLZ: return LowerCTLZ(Op, DAG);
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case ISD::CTTZ: return LowerCTTZ(Op, DAG);
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case ISD::SADDO: return LowerXADDO(Op, DAG, ISD::SADDO);
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case ISD::UADDO: return LowerXADDO(Op, DAG, ISD::UADDO);
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// FIXME: REMOVE THIS WHEN LegalizeDAGTypes lands.
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case ISD::READCYCLECOUNTER:
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@ -592,6 +592,8 @@ namespace llvm {
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SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG);
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SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG);
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SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG);
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SDValue LowerXADDO(SDValue Op, SelectionDAG &DAG, ISD::NodeType NTy);
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SDValue LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG);
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SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG);
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SDValue LowerATOMIC_BINARY_64(SDValue Op, SelectionDAG &DAG,
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