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[mips] Reformat some TableGen definitions. NFC.
Summary: Separated some instruction and pseudo-instruction definitions from InstAlias definitions, added banner for pseudo-instructions and removed a redundant whitespace from a pseudo-instruction definition. No functional change. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7552 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230327 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -419,6 +419,14 @@ def VMULU : ArithLogicR<"vmulu", GPR64Opnd, 0, II_DMUL>,
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}
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/// Move between CPU and coprocessor registers
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let DecoderNamespace = "Mips64", Predicates = [HasMips64] in {
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def DMFC0 : MFC3OP<"dmfc0", GPR64Opnd>, MFC3OP_FM<0x10, 1>;
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def DMTC0 : MFC3OP<"dmtc0", GPR64Opnd>, MFC3OP_FM<0x10, 5>, ISA_MIPS3;
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def DMFC2 : MFC3OP<"dmfc2", GPR64Opnd>, MFC3OP_FM<0x12, 1>, ISA_MIPS3;
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def DMTC2 : MFC3OP<"dmtc2", GPR64Opnd>, MFC3OP_FM<0x12, 5>, ISA_MIPS3;
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}
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//===----------------------------------------------------------------------===//
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// Arbitrary patterns that map to one or more instructions
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//===----------------------------------------------------------------------===//
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@ -579,19 +587,6 @@ def : MipsInstAlias<"dsrl $rd, $rt, $rs",
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(DSRLV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>,
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ISA_MIPS3;
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class LoadImm64< string instr_asm, Operand Od, RegisterOperand RO> :
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MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm64),
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!strconcat(instr_asm, "\t$rt, $imm64")> ;
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def LoadImm64Reg : LoadImm64<"dli", imm64, GPR64Opnd>;
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/// Move between CPU and coprocessor registers
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let DecoderNamespace = "Mips64", Predicates = [HasMips64] in {
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def DMFC0 : MFC3OP<"dmfc0", GPR64Opnd>, MFC3OP_FM<0x10, 1>;
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def DMTC0 : MFC3OP<"dmtc0", GPR64Opnd>, MFC3OP_FM<0x10, 5>, ISA_MIPS3;
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def DMFC2 : MFC3OP<"dmfc2", GPR64Opnd>, MFC3OP_FM<0x12, 1>, ISA_MIPS3;
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def DMTC2 : MFC3OP<"dmtc2", GPR64Opnd>, MFC3OP_FM<0x12, 5>, ISA_MIPS3;
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}
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// Two operand (implicit 0 selector) versions:
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def : MipsInstAlias<"dmfc0 $rt, $rd", (DMFC0 GPR64Opnd:$rt, GPR64Opnd:$rd, 0), 0>;
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def : MipsInstAlias<"dmtc0 $rt, $rd", (DMTC0 GPR64Opnd:$rt, GPR64Opnd:$rd, 0), 0>;
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@ -604,3 +599,12 @@ def : MipsInstAlias<"syncs", (SYNC 0x6), 0>;
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def : MipsInstAlias<"syncw", (SYNC 0x4), 0>;
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def : MipsInstAlias<"syncws", (SYNC 0x5), 0>;
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}
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//===----------------------------------------------------------------------===//
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// Assembler Pseudo Instructions
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//===----------------------------------------------------------------------===//
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class LoadImm64<string instr_asm, Operand Od, RegisterOperand RO> :
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MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm64),
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!strconcat(instr_asm, "\t$rt, $imm64")> ;
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def LoadImm64Reg : LoadImm64<"dli", imm64, GPR64Opnd>;
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@ -1639,7 +1639,7 @@ def : MipsInstAlias<"sync",
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// Assembler Pseudo Instructions
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//===----------------------------------------------------------------------===//
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class LoadImm32< string instr_asm, Operand Od, RegisterOperand RO> :
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class LoadImm32<string instr_asm, Operand Od, RegisterOperand RO> :
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MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
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!strconcat(instr_asm, "\t$rt, $imm32")> ;
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def LoadImm32Reg : LoadImm32<"li", uimm5, GPR32Opnd>;
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