From 41f28722ef6e3de90e7631bca2021d41b931cf00 Mon Sep 17 00:00:00 2001 From: Zoran Jovanovic Date: Wed, 24 Jun 2015 10:32:16 +0000 Subject: [PATCH] [mips][microMIPS] Implement BREAK, EHB and EI instructions http://reviews.llvm.org/D10090 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240531 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/MicroMips32r6InstrFormats.td | 32 ++++++++++++++++++++ lib/Target/Mips/MicroMips32r6InstrInfo.td | 19 ++++++++++++ lib/Target/Mips/MicroMipsInstrInfo.td | 4 +++ lib/Target/Mips/MipsInstrInfo.td | 10 ++++-- test/MC/Disassembler/Mips/micromips.txt | 4 +++ test/MC/Disassembler/Mips/micromips32r6.txt | 12 ++++++++ test/MC/Disassembler/Mips/micromips_le.txt | 4 +++ test/MC/Mips/micromips32r6/invalid.s | 6 ++++ test/MC/Mips/micromips32r6/valid.s | 7 +++++ 9 files changed, 96 insertions(+), 2 deletions(-) create mode 100644 test/MC/Mips/micromips32r6/invalid.s diff --git a/lib/Target/Mips/MicroMips32r6InstrFormats.td b/lib/Target/Mips/MicroMips32r6InstrFormats.td index 78ba76d27cb..8b15f6df48f 100644 --- a/lib/Target/Mips/MicroMips32r6InstrFormats.td +++ b/lib/Target/Mips/MicroMips32r6InstrFormats.td @@ -240,3 +240,35 @@ class ERETNC_FM_MMR6 : MMR6Arch { let Inst{15-6} = 0x3cd; let Inst{5-0} = 0x3c; } + +class BREAK_MMR6_ENC : MMR6Arch { + bits<10> code_1; + bits<10> code_2; + bits<32> Inst; + let Inst{31-26} = 0x0; + let Inst{25-16} = code_1; + let Inst{15-6} = code_2; + let Inst{5-0} = 0x07; +} + +class BARRIER_MMR6_ENC op> : MMR6Arch { + bits<32> Inst; + + let Inst{31-26} = 0x0; + let Inst{25-21} = 0x0; + let Inst{20-16} = 0x0; + let Inst{15-11} = op; + let Inst{10-6} = 0x0; + let Inst{5-0} = 0x0; +} + +class EIDI_MMR6_ENC funct> : MMR6Arch { + bits<32> Inst; + bits<5> rt; // Actually rs but we're sharing code with the standard encodings which call it rt + + let Inst{31-26} = 0x00; + let Inst{25-21} = 0x00; + let Inst{20-16} = rt; + let Inst{15-6} = funct; + let Inst{5-0} = 0x3c; +} diff --git a/lib/Target/Mips/MicroMips32r6InstrInfo.td b/lib/Target/Mips/MicroMips32r6InstrInfo.td index ed71c3d9b5f..769c0bbebe3 100644 --- a/lib/Target/Mips/MicroMips32r6InstrInfo.td +++ b/lib/Target/Mips/MicroMips32r6InstrInfo.td @@ -29,6 +29,7 @@ class AUI_MMR6_ENC : AUI_FM_MMR6; class BALC_MMR6_ENC : BRANCH_OFF26_FM<0b101101>; class BC_MMR6_ENC : BRANCH_OFF26_FM<0b100101>; class BITSWAP_MMR6_ENC : POOL32A_BITSWAP_FM_MMR6<0b101100>; +class BRK_MMR6_ENC : BREAK_MMR6_ENC<"break">; class BEQZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<0b011101>; class BNEZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<0b011111>; class BGTZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<0b111000>; @@ -40,6 +41,8 @@ class CLO_MMR6_ENC : POOL32A_2R_FM_MMR6<0b0100101100>; class CLZ_MMR6_ENC : SPECIAL_2R_FM_MMR6<0b010000>; class DIV_MMR6_ENC : ARITH_FM_MMR6<"div", 0x118>; class DIVU_MMR6_ENC : ARITH_FM_MMR6<"divu", 0x198>; +class EHB_MMR6_ENC : BARRIER_MMR6_ENC<"ehb", 0x3>; +class EI_MMR6_ENC : EIDI_MMR6_ENC<"ei", 0x15d>; class ERET_MMR6_ENC : ERET_FM_MMR6<"eret">; class ERETNC_MMR6_ENC : ERETNC_FM_MMR6<"eretnc">; class JIALC_MMR6_ENC : JMP_IDX_COMPACT_FM<0b100000>; @@ -144,6 +147,8 @@ class BITSWAP_MMR6_DESC_BASE class BITSWAP_MMR6_DESC : BITSWAP_MMR6_DESC_BASE<"bitswap", GPR32Opnd>; +class BRK_MMR6_DESC : BRK_FT<"break">; + class CACHE_HINT_MMR6_DESC : MMR6Arch { dag OutOperandList = (outs); @@ -166,6 +171,9 @@ class CLO_CLZ_MMR6_DESC_BASE class CLO_MMR6_DESC : CLO_CLZ_MMR6_DESC_BASE<"clo", GPR32Opnd>; class CLZ_MMR6_DESC : CLO_CLZ_MMR6_DESC_BASE<"clz", GPR32Opnd>; +class EHB_MMR6_DESC : Barrier<"ehb">; +class EI_MMR6_DESC : DEI_FT<"ei", GPR32Opnd>; + class ERET_MMR6_DESC : ER_FT<"eret">; class ERETNC_MMR6_DESC : ER_FT<"eretnc">; @@ -302,11 +310,14 @@ def BLTZALC_MMR6 : R6MMR6Rel, BLTZALC_MMR6_ENC, BLTZALC_MMR6_DESC, ISA_MICROMIPS32R6; def BNEZALC_MMR6 : R6MMR6Rel, BNEZALC_MMR6_ENC, BNEZALC_MMR6_DESC, ISA_MICROMIPS32R6; +def BREAK_MMR6 : StdMMR6Rel, BRK_MMR6_DESC, BRK_MMR6_ENC, ISA_MICROMIPS32R6; def CACHE_MMR6 : R6MMR6Rel, CACHE_MMR6_ENC, CACHE_MMR6_DESC, ISA_MICROMIPS32R6; def CLO_MMR6 : R6MMR6Rel, CLO_MMR6_ENC, CLO_MMR6_DESC, ISA_MICROMIPS32R6; def CLZ_MMR6 : R6MMR6Rel, CLZ_MMR6_ENC, CLZ_MMR6_DESC, ISA_MICROMIPS32R6; def DIV_MMR6 : R6MMR6Rel, DIV_MMR6_DESC, DIV_MMR6_ENC, ISA_MICROMIPS32R6; def DIVU_MMR6 : R6MMR6Rel, DIVU_MMR6_DESC, DIVU_MMR6_ENC, ISA_MICROMIPS32R6; +def EHB_MMR6 : StdMMR6Rel, EHB_MMR6_DESC, EHB_MMR6_ENC, ISA_MICROMIPS32R6; +def EI_MMR6 : StdMMR6Rel, EI_MMR6_DESC, EI_MMR6_ENC, ISA_MICROMIPS32R6; def ERET_MMR6 : R6MMR6Rel, ERET_MMR6_DESC, ERET_MMR6_ENC, ISA_MICROMIPS32R6; def ERETNC_MMR6 : R6MMR6Rel, ERETNC_MMR6_DESC, ERETNC_MMR6_ENC, ISA_MICROMIPS32R6; @@ -335,3 +346,11 @@ def SUBU_MMR6 : StdMMR6Rel, SUBU_MMR6_DESC, SUBU_MMR6_ENC, ISA_MICROMIPS32R6; def XOR_MMR6 : StdMMR6Rel, XOR_MMR6_DESC, XOR_MMR6_ENC, ISA_MICROMIPS32R6; def XORI_MMR6 : StdMMR6Rel, XORI_MMR6_DESC, XORI_MMR6_ENC, ISA_MICROMIPS32R6; } + +//===----------------------------------------------------------------------===// +// +// MicroMips instruction aliases +// +//===----------------------------------------------------------------------===// + +def : MipsInstAlias<"ei", (EI_MMR6 ZERO), 1>, ISA_MICROMIPS32R6; diff --git a/lib/Target/Mips/MicroMipsInstrInfo.td b/lib/Target/Mips/MicroMipsInstrInfo.td index 2aab739dbd2..39393840c6f 100644 --- a/lib/Target/Mips/MicroMipsInstrInfo.td +++ b/lib/Target/Mips/MicroMipsInstrInfo.td @@ -934,3 +934,7 @@ class UncondBranchMMPseudo : def : MipsInstAlias<"nop", (SLL_MM ZERO, ZERO, 0), 1>; def : MipsInstAlias<"nop", (MOVE16_MM ZERO, ZERO), 1>; } + +let Predicates = [InMicroMips] in { +def : MipsInstAlias<"ei", (EI_MM ZERO), 1>, ISA_MIPS32R2; +} diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td index 85318bbe43e..17f9f290d64 100644 --- a/lib/Target/Mips/MipsInstrInfo.td +++ b/lib/Target/Mips/MipsInstrInfo.td @@ -1278,7 +1278,9 @@ def TTLTIU : MMRel, TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM<0xb>, def TNEI : MMRel, TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM<0xe>, ISA_MIPS2_NOT_32R6_64R6; -def BREAK : MMRel, BRK_FT<"break">, BRK_FM<0xd>; +let AdditionalPredicates = [NotInMicroMips] in { +def BREAK : MMRel, StdMMR6Rel, BRK_FT<"break">, BRK_FM<0xd>; +} def SYSCALL : MMRel, SYS_FT<"syscall">, SYS_FM<0xc>; def TRAP : TrapBase; def SDBBP : MMRel, SYS_FT<"sdbbp">, SDBBP_FM, ISA_MIPS32_NOT_32R6_64R6; @@ -1288,7 +1290,9 @@ def ERET : MMRel, ER_FT<"eret">, ER_FM<0x18>, INSN_MIPS3_32; } def DERET : MMRel, ER_FT<"deret">, ER_FM<0x1f>, ISA_MIPS32; -def EI : MMRel, DEI_FT<"ei", GPR32Opnd>, EI_FM<1>, ISA_MIPS32R2; +let AdditionalPredicates = [NotInMicroMips] in { +def EI : MMRel, StdMMR6Rel, DEI_FT<"ei", GPR32Opnd>, EI_FM<1>, ISA_MIPS32R2; +} def DI : MMRel, DEI_FT<"di", GPR32Opnd>, EI_FM<0>, ISA_MIPS32R2; let EncodingPredicates = [], // FIXME: Lack of HasStdEnc is probably a bug @@ -1623,7 +1627,9 @@ def : MipsInstAlias<"syscall", (SYSCALL 0), 1>; def : MipsInstAlias<"break", (BREAK 0, 0), 1>; def : MipsInstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>; +let AdditionalPredicates = [NotInMicroMips] in { def : MipsInstAlias<"ei", (EI ZERO), 1>, ISA_MIPS32R2; +} def : MipsInstAlias<"di", (DI ZERO), 1>, ISA_MIPS32R2; def : MipsInstAlias<"teq $rs, $rt", diff --git a/test/MC/Disassembler/Mips/micromips.txt b/test/MC/Disassembler/Mips/micromips.txt index 637e88928e7..5809ac28113 100644 --- a/test/MC/Disassembler/Mips/micromips.txt +++ b/test/MC/Disassembler/Mips/micromips.txt @@ -336,3 +336,7 @@ 0x46 0xce # CHECK: sdbbp16 14 0x84 0x34 # CHECK: movep $5, $6, $2, $3 + +0x00 0x00 0x57 0x7c # CHECK: ei + +0x00 0x0a 0x57 0x7c # CHECK: ei $10 diff --git a/test/MC/Disassembler/Mips/micromips32r6.txt b/test/MC/Disassembler/Mips/micromips32r6.txt index 47c4d080f0a..5bedf6ed050 100644 --- a/test/MC/Disassembler/Mips/micromips32r6.txt +++ b/test/MC/Disassembler/Mips/micromips32r6.txt @@ -38,6 +38,12 @@ 0x00 0x44 0x0b 0x3c # CHECK: bitswap $4, $2 +0x00 0x00 0x00 0x07 # CHECK: break + +0x00 0x07 0x00 0x07 # CHECK: break 7 + +0x00 0x07 0x01 0x47 # CHECK: break 7, 5 + 0x20 0x25 0x60 0x08 # CHECK: cache 1, 8($5) 0x01 0x65 0x4b 0x3c # CHECK: clo $11, $5 @@ -48,6 +54,12 @@ 0x00 0xa4 0x19 0x98 # CHECK: divu $3, $4, $5 +0x00 0x00 0x18 0x00 # CHECK: ehb + +0x00 0x00 0x57 0x7c # CHECK: ei + +0x00 0x0a 0x57 0x7c # CHECK: ei $10 + 0x00 0x00 0xf3 0x7c # CHECK: eret 0x00 0x01 0xf3 0x7c # CHECK: eretnc diff --git a/test/MC/Disassembler/Mips/micromips_le.txt b/test/MC/Disassembler/Mips/micromips_le.txt index 3899c510330..3058bd06106 100644 --- a/test/MC/Disassembler/Mips/micromips_le.txt +++ b/test/MC/Disassembler/Mips/micromips_le.txt @@ -336,3 +336,7 @@ 0xce 0x46 # CHECK: sdbbp16 14 0x34 0x84 # CHECK: movep $5, $6, $2, $3 + +0x00 0x00 0x7c 0x57 # CHECK: ei + +0x0a 0x00 0x7c 0x57 # CHECK: ei $10 diff --git a/test/MC/Mips/micromips32r6/invalid.s b/test/MC/Mips/micromips32r6/invalid.s new file mode 100644 index 00000000000..8ba787ae1aa --- /dev/null +++ b/test/MC/Mips/micromips32r6/invalid.s @@ -0,0 +1,6 @@ +# RUN: not llvm-mc %s -triple=mips -show-encoding -mcpu=mips32r6 -mattr=micromips 2>%t1 +# RUN: FileCheck %s < %t1 + + break 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + break 1023, 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + ei $32 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction diff --git a/test/MC/Mips/micromips32r6/valid.s b/test/MC/Mips/micromips32r6/valid.s index 94e19f2c46f..a4829b945a2 100644 --- a/test/MC/Mips/micromips32r6/valid.s +++ b/test/MC/Mips/micromips32r6/valid.s @@ -20,11 +20,18 @@ balc 14572256 # CHECK: balc 14572256 # encoding: [0xb4,0x37,0x96,0xb8] bc 14572256 # CHECK: bc 14572256 # encoding: [0x94,0x37,0x96,0xb8] bitswap $4, $2 # CHECK: bitswap $4, $2 # encoding: [0x00,0x44,0x0b,0x3c] + break # CHECK: break # encoding: [0x00,0x00,0x00,0x07] + break 7 # CHECK: break 7 # encoding: [0x00,0x07,0x00,0x07] + break 7, 5 # CHECK: break 7, 5 # encoding: [0x00,0x07,0x01,0x47] cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0x20,0x25,0x60,0x08] clo $11, $a1 # CHECK: clo $11, $5 # encoding: [0x01,0x65,0x4b,0x3c] clz $sp, $gp # CHECK: clz $sp, $gp # encoding: [0x03,0x80,0xe8,0x50] div $3, $4, $5 # CHECK: div $3, $4, $5 # encoding: [0x00,0xa4,0x19,0x18] divu $3, $4, $5 # CHECK: divu $3, $4, $5 # encoding: [0x00,0xa4,0x19,0x98] + ehb # CHECK: ehb # encoding: [0x00,0x00,0x18,0x00] + ei # CHECK: ei # encoding: [0x00,0x00,0x57,0x7c] + ei $0 # CHECK: ei # encoding: [0x00,0x00,0x57,0x7c] + ei $10 # CHECK: ei $10 # encoding: [0x00,0x0a,0x57,0x7c] eret # CHECK: eret # encoding: [0x00,0x00,0xf3,0x7c] eretnc # CHECK: eretnc # encoding: [0x00,0x01,0xf3,0x7c] jialc $5, 256 # CHECK: jialc $5, 256 # encoding: [0x80,0x05,0x01,0x00]