switch TargetLowering::getConstraintType to take the entire constraint,

not just the first letter.  No functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35322 91177308-0d34-0410-b5e6-96231b3b80d8

include/llvm/Target/TargetLowering.h

@@ -806,9 +806,9 @@ public:
     C_Unknown              // Unsupported constraint.
   };
   
-  /// getConstraintType - Given a constraint letter, return the type of
+  /// getConstraintType - Given a constraint, return the type of constraint it
-  /// constraint it is for this target.
+  /// is for this target.
-  virtual ConstraintType getConstraintType(char ConstraintLetter) const;
+  virtual ConstraintType getConstraintType(const std::string &Constraint) const;
   
   
   /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"),

lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

@@ -2633,9 +2633,9 @@ static std::string GetMostGeneralConstraint(std::vector<std::string> &C,
   std::string *Current = &C[0];
   // If we have multiple constraints, try to pick the most general one ahead
   // of time.  This isn't a wonderful solution, but handles common cases.
-  TargetLowering::ConstraintType Flavor = TLI.getConstraintType(Current[0][0]);
+  TargetLowering::ConstraintType Flavor = TLI.getConstraintType(Current[0]);
   for (unsigned j = 1, e = C.size(); j != e; ++j) {
-    TargetLowering::ConstraintType ThisFlavor = TLI.getConstraintType(C[j][0]);
+    TargetLowering::ConstraintType ThisFlavor = TLI.getConstraintType(C[j]);
     if (getConstraintGenerality(ThisFlavor) > 
         getConstraintGenerality(Flavor)) {
       // This constraint letter is more general than the previous one,
@@ -2748,7 +2748,7 @@ void SelectionDAGLowering::visitInlineAsm(CallInst &I) {
     case InlineAsm::isOutput: {
       TargetLowering::ConstraintType CTy = TargetLowering::C_RegisterClass;
       if (ConstraintCode.size() == 1)   // not a physreg name.
-        CTy = TLI.getConstraintType(ConstraintCode[0]);
+        CTy = TLI.getConstraintType(ConstraintCode);
       
       if (CTy == TargetLowering::C_Memory) {
         // Memory output.
@@ -2863,7 +2863,7 @@ void SelectionDAGLowering::visitInlineAsm(CallInst &I) {
       
       TargetLowering::ConstraintType CTy = TargetLowering::C_RegisterClass;
       if (ConstraintCode.size() == 1)   // not a physreg name.
-        CTy = TLI.getConstraintType(ConstraintCode[0]);
+        CTy = TLI.getConstraintType(ConstraintCode);
         
       if (CTy == TargetLowering::C_Other) {
         InOperandVal = TLI.isOperandValidForConstraint(InOperandVal,

lib/CodeGen/SelectionDAG/TargetLowering.cpp

@@ -1828,10 +1828,11 @@ PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
 //===----------------------------------------------------------------------===//
 
 TargetLowering::ConstraintType
-TargetLowering::getConstraintType(char ConstraintLetter) const {
+TargetLowering::getConstraintType(const std::string &Constraint) const {
   // FIXME: lots more standard ones to handle.
-  switch (ConstraintLetter) {
+  if (Constraint.size() == 1) {
-  default: return C_Unknown;
+    switch (Constraint[0]) {
+    default: break;
     case 'r': return C_RegisterClass;
     case 'm':    // memory
     case 'o':    // offsetable
@@ -1851,6 +1852,9 @@ TargetLowering::getConstraintType(char ConstraintLetter) const {
       return C_Other;
     }
   }
+  // TODO: Handle registers.
+  return C_Unknown;
+}
 
 /// isOperandValidForConstraint - Return the specified operand (possibly
 /// modified) if the specified SDOperand is valid for the specified target

lib/Target/ARM/ARMISelLowering.cpp

@@ -1550,13 +1550,15 @@ void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
 /// getConstraintType - Given a constraint letter, return the type of
 /// constraint it is for this target.
 ARMTargetLowering::ConstraintType
-ARMTargetLowering::getConstraintType(char ConstraintLetter) const {
+ARMTargetLowering::getConstraintType(const std::string &Constraint) const {
-  switch (ConstraintLetter) {
+  if (Constraint.size() == 1) {
-    case 'l':
+    switch (Constraint[0]) {
-      return C_RegisterClass;
+    default:  break;
-    default: return TargetLowering::getConstraintType(ConstraintLetter);
+    case 'l': return C_RegisterClass;
     }
   }
+  return TargetLowering::getConstraintType(Constraint);
+}
 
 std::pair<unsigned, const TargetRegisterClass*> 
 ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,

lib/Target/ARM/ARMISelLowering.h

@@ -133,7 +133,7 @@ namespace llvm {
                                                 uint64_t &KnownZero, 
                                                 uint64_t &KnownOne,
                                                 unsigned Depth) const;
-    ConstraintType getConstraintType(char ConstraintLetter) const;
+    ConstraintType getConstraintType(const std::string &Constraint) const;
     std::pair<unsigned, const TargetRegisterClass*> 
       getRegForInlineAsmConstraint(const std::string &Constraint,
                                    MVT::ValueType VT) const;

lib/Target/Alpha/AlphaISelLowering.cpp

@@ -571,14 +571,16 @@ SDOperand AlphaTargetLowering::CustomPromoteOperation(SDOperand Op,
 /// getConstraintType - Given a constraint letter, return the type of
 /// constraint it is for this target.
 AlphaTargetLowering::ConstraintType 
-AlphaTargetLowering::getConstraintType(char ConstraintLetter) const {
+AlphaTargetLowering::getConstraintType(const std::string &Constraint) const {
-  switch (ConstraintLetter) {
+  if (Constraint.size() == 1) {
+    switch (Constraint[0]) {
     default: break;
     case 'f':
     case 'r':
       return C_RegisterClass;
     }
-  return TargetLowering::getConstraintType(ConstraintLetter);
+  }
+  return TargetLowering::getConstraintType(Constraint);
 }
 
 std::vector<unsigned> AlphaTargetLowering::

lib/Target/Alpha/AlphaISelLowering.h

@@ -81,7 +81,7 @@ namespace llvm {
                 bool isVarArg, unsigned CC, bool isTailCall, SDOperand Callee, 
                 ArgListTy &Args, SelectionDAG &DAG);
 
-    ConstraintType getConstraintType(char ConstraintLetter) const;
+    ConstraintType getConstraintType(const std::string &Constraint) const;
 
     std::vector<unsigned> 
       getRegClassForInlineAsmConstraint(const std::string &Constraint,

lib/Target/PowerPC/PPCISelLowering.cpp

@@ -3105,11 +3105,12 @@ void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
 }
 
 
-/// getConstraintType - Given a constraint letter, return the type of
+/// getConstraintType - Given a constraint, return the type of
 /// constraint it is for this target.
 PPCTargetLowering::ConstraintType 
-PPCTargetLowering::getConstraintType(char ConstraintLetter) const {
+PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
-  switch (ConstraintLetter) {
+  if (Constraint.size() == 1) {
+    switch (Constraint[0]) {
     default: break;
     case 'b':
     case 'r':
@@ -3118,7 +3119,8 @@ PPCTargetLowering::getConstraintType(char ConstraintLetter) const {
     case 'y':
       return C_RegisterClass;
     }
-  return TargetLowering::getConstraintType(ConstraintLetter);
+  }
+  return TargetLowering::getConstraintType(Constraint);
 }
 
 std::pair<unsigned, const TargetRegisterClass*> 

lib/Target/PowerPC/PPCISelLowering.h

@@ -229,7 +229,7 @@ namespace llvm {
     virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
                                                        MachineBasicBlock *MBB);
     
-    ConstraintType getConstraintType(char ConstraintLetter) const;
+    ConstraintType getConstraintType(const std::string &Constraint) const;
     std::pair<unsigned, const TargetRegisterClass*> 
       getRegForInlineAsmConstraint(const std::string &Constraint,
                                    MVT::ValueType VT) const;

lib/Target/X86/X86ISelLowering.cpp

@@ -4521,8 +4521,9 @@ SDOperand X86TargetLowering::PerformDAGCombine(SDNode *N,
 /// getConstraintType - Given a constraint letter, return the type of
 /// constraint it is for this target.
 X86TargetLowering::ConstraintType
-X86TargetLowering::getConstraintType(char ConstraintLetter) const {
+X86TargetLowering::getConstraintType(const std::string &Constraint) const {
-  switch (ConstraintLetter) {
+  if (Constraint.size() == 1) {
+    switch (Constraint[0]) {
     case 'A':
     case 'r':
     case 'R':
@@ -4532,9 +4533,12 @@ X86TargetLowering::getConstraintType(char ConstraintLetter) const {
     case 'x':
     case 'Y':
       return C_RegisterClass;
-  default: return TargetLowering::getConstraintType(ConstraintLetter);
+    default:
+      break;
     }
   }
+  return TargetLowering::getConstraintType(Constraint);
+}
 
 /// isOperandValidForConstraint - Return the specified operand (possibly
 /// modified) if the specified SDOperand is valid for the specified target

lib/Target/X86/X86ISelLowering.h

@@ -316,7 +316,7 @@ namespace llvm {
     
     SDOperand getReturnAddressFrameIndex(SelectionDAG &DAG);
 
-    ConstraintType getConstraintType(char ConstraintLetter) const;
+    ConstraintType getConstraintType(const std::string &Constraint) const;
      
     std::vector<unsigned> 
       getRegClassForInlineAsmConstraint(const std::string &Constraint,