mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-08 18:30:04 +00:00
[x86] Mechanically update a bunch of tests' check lines using the latest
version of the script. Changes include: - Using the VEX prefix - Skipping more detail when we have useful shuffle comments to match - Matching more shuffle comments that have been added to the printer (yay!) - Matching the destination registers of some AVX instructions - Stripping trailing whitespace that crept in - Fixing indentation issues Nothing interesting going on here. I'm just trying really hard to ensure these changes don't show up in the diffs with actual changes to the backend. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228132 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chandler Carruth
parent
f95422a37c
commit
424a198c30
@ -38,13 +38,13 @@ entry:
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define <4 x float> @vsel_float2(<4 x float> %v1, <4 x float> %v2) {
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; SSE2-LABEL: vsel_float2:
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; SSE2: # BB#0: # %entry
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; SSE2-NEXT: movss %xmm0, %xmm1
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; SSE2-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
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; SSE2-NEXT: movaps %xmm1, %xmm0
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; SSE2-NEXT: retq
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;
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; SSSE3-LABEL: vsel_float2:
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; SSSE3: # BB#0: # %entry
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; SSSE3-NEXT: movss %xmm0, %xmm1
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; SSSE3-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
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; SSSE3-NEXT: movaps %xmm1, %xmm0
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; SSSE3-NEXT: retq
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;
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@ -55,7 +55,7 @@ define <4 x float> @vsel_float2(<4 x float> %v1, <4 x float> %v2) {
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;
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; AVX-LABEL: vsel_float2:
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; AVX: # BB#0: # %entry
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; AVX-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
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; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
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; AVX-NEXT: retq
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entry:
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%vsel = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x float> %v1, <4 x float> %v2
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@ -167,13 +167,13 @@ entry:
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define <2 x double> @vsel_double(<2 x double> %v1, <2 x double> %v2) {
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; SSE2-LABEL: vsel_double:
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; SSE2: # BB#0: # %entry
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; SSE2-NEXT: movsd %xmm0, %xmm1
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; SSE2-NEXT: movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1]
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; SSE2-NEXT: movaps %xmm1, %xmm0
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; SSE2-NEXT: retq
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;
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; SSSE3-LABEL: vsel_double:
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; SSSE3: # BB#0: # %entry
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; SSSE3-NEXT: movsd %xmm0, %xmm1
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; SSSE3-NEXT: movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1]
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; SSSE3-NEXT: movaps %xmm1, %xmm0
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; SSSE3-NEXT: retq
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;
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@ -194,13 +194,13 @@ entry:
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define <2 x i64> @vsel_i64(<2 x i64> %v1, <2 x i64> %v2) {
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; SSE2-LABEL: vsel_i64:
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; SSE2: # BB#0: # %entry
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; SSE2-NEXT: movsd %xmm0, %xmm1
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; SSE2-NEXT: movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1]
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; SSE2-NEXT: movaps %xmm1, %xmm0
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; SSE2-NEXT: retq
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;
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; SSSE3-LABEL: vsel_i64:
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; SSSE3: # BB#0: # %entry
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; SSSE3-NEXT: movsd %xmm0, %xmm1
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; SSSE3-NEXT: movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1]
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; SSSE3-NEXT: movaps %xmm1, %xmm0
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; SSSE3-NEXT: retq
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;
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@ -291,16 +291,16 @@ entry:
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define <8 x float> @vsel_float8(<8 x float> %v1, <8 x float> %v2) {
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; SSE2-LABEL: vsel_float8:
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; SSE2: # BB#0: # %entry
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; SSE2-NEXT: movss %xmm0, %xmm2
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; SSE2-NEXT: movss %xmm1, %xmm3
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; SSE2-NEXT: movss {{.*#+}} xmm2 = xmm0[0],xmm2[1,2,3]
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; SSE2-NEXT: movss {{.*#+}} xmm3 = xmm1[0],xmm3[1,2,3]
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; SSE2-NEXT: movaps %xmm2, %xmm0
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; SSE2-NEXT: movaps %xmm3, %xmm1
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; SSE2-NEXT: retq
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;
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; SSSE3-LABEL: vsel_float8:
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; SSSE3: # BB#0: # %entry
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; SSSE3-NEXT: movss %xmm0, %xmm2
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; SSSE3-NEXT: movss %xmm1, %xmm3
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; SSSE3-NEXT: movss {{.*#+}} xmm2 = xmm0[0],xmm2[1,2,3]
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; SSSE3-NEXT: movss {{.*#+}} xmm3 = xmm1[0],xmm3[1,2,3]
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; SSSE3-NEXT: movaps %xmm2, %xmm0
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; SSSE3-NEXT: movaps %xmm3, %xmm1
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; SSSE3-NEXT: retq
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@ -323,16 +323,16 @@ entry:
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define <8 x i32> @vsel_i328(<8 x i32> %v1, <8 x i32> %v2) {
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; SSE2-LABEL: vsel_i328:
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; SSE2: # BB#0: # %entry
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; SSE2-NEXT: movss %xmm0, %xmm2
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; SSE2-NEXT: movss %xmm1, %xmm3
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; SSE2-NEXT: movss {{.*#+}} xmm2 = xmm0[0],xmm2[1,2,3]
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; SSE2-NEXT: movss {{.*#+}} xmm3 = xmm1[0],xmm3[1,2,3]
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; SSE2-NEXT: movaps %xmm2, %xmm0
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; SSE2-NEXT: movaps %xmm3, %xmm1
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; SSE2-NEXT: retq
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;
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; SSSE3-LABEL: vsel_i328:
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; SSSE3: # BB#0: # %entry
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; SSSE3-NEXT: movss %xmm0, %xmm2
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; SSSE3-NEXT: movss %xmm1, %xmm3
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; SSSE3-NEXT: movss {{.*#+}} xmm2 = xmm0[0],xmm2[1,2,3]
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; SSSE3-NEXT: movss {{.*#+}} xmm3 = xmm1[0],xmm3[1,2,3]
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; SSSE3-NEXT: movaps %xmm2, %xmm0
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; SSSE3-NEXT: movaps %xmm3, %xmm1
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; SSSE3-NEXT: retq
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@ -360,8 +360,8 @@ entry:
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define <8 x double> @vsel_double8(<8 x double> %v1, <8 x double> %v2) {
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; SSE2-LABEL: vsel_double8:
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; SSE2: # BB#0: # %entry
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; SSE2-NEXT: movsd %xmm0, %xmm4
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; SSE2-NEXT: movsd %xmm2, %xmm6
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; SSE2-NEXT: movsd {{.*#+}} xmm4 = xmm0[0],xmm4[1]
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; SSE2-NEXT: movsd {{.*#+}} xmm6 = xmm2[0],xmm6[1]
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; SSE2-NEXT: movaps %xmm4, %xmm0
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; SSE2-NEXT: movaps %xmm5, %xmm1
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; SSE2-NEXT: movaps %xmm6, %xmm2
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@ -370,8 +370,8 @@ define <8 x double> @vsel_double8(<8 x double> %v1, <8 x double> %v2) {
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;
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; SSSE3-LABEL: vsel_double8:
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; SSSE3: # BB#0: # %entry
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; SSSE3-NEXT: movsd %xmm0, %xmm4
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; SSSE3-NEXT: movsd %xmm2, %xmm6
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; SSSE3-NEXT: movsd {{.*#+}} xmm4 = xmm0[0],xmm4[1]
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; SSSE3-NEXT: movsd {{.*#+}} xmm6 = xmm2[0],xmm6[1]
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; SSSE3-NEXT: movaps %xmm4, %xmm0
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; SSSE3-NEXT: movaps %xmm5, %xmm1
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; SSSE3-NEXT: movaps %xmm6, %xmm2
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@ -399,8 +399,8 @@ entry:
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define <8 x i64> @vsel_i648(<8 x i64> %v1, <8 x i64> %v2) {
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; SSE2-LABEL: vsel_i648:
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; SSE2: # BB#0: # %entry
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; SSE2-NEXT: movsd %xmm0, %xmm4
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; SSE2-NEXT: movsd %xmm2, %xmm6
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; SSE2-NEXT: movsd {{.*#+}} xmm4 = xmm0[0],xmm4[1]
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; SSE2-NEXT: movsd {{.*#+}} xmm6 = xmm2[0],xmm6[1]
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; SSE2-NEXT: movaps %xmm4, %xmm0
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; SSE2-NEXT: movaps %xmm5, %xmm1
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; SSE2-NEXT: movaps %xmm6, %xmm2
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@ -409,8 +409,8 @@ define <8 x i64> @vsel_i648(<8 x i64> %v1, <8 x i64> %v2) {
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;
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; SSSE3-LABEL: vsel_i648:
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; SSSE3: # BB#0: # %entry
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; SSSE3-NEXT: movsd %xmm0, %xmm4
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; SSSE3-NEXT: movsd %xmm2, %xmm6
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; SSSE3-NEXT: movsd {{.*#+}} xmm4 = xmm0[0],xmm4[1]
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; SSSE3-NEXT: movsd {{.*#+}} xmm6 = xmm2[0],xmm6[1]
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; SSSE3-NEXT: movaps %xmm4, %xmm0
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; SSSE3-NEXT: movaps %xmm5, %xmm1
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; SSSE3-NEXT: movaps %xmm6, %xmm2
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@ -444,16 +444,16 @@ entry:
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define <4 x double> @vsel_double4(<4 x double> %v1, <4 x double> %v2) {
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; SSE2-LABEL: vsel_double4:
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; SSE2: # BB#0: # %entry
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; SSE2-NEXT: movsd %xmm0, %xmm2
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; SSE2-NEXT: movsd %xmm1, %xmm3
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; SSE2-NEXT: movsd {{.*#+}} xmm2 = xmm0[0],xmm2[1]
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; SSE2-NEXT: movsd {{.*#+}} xmm3 = xmm1[0],xmm3[1]
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; SSE2-NEXT: movaps %xmm2, %xmm0
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; SSE2-NEXT: movaps %xmm3, %xmm1
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; SSE2-NEXT: retq
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;
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; SSSE3-LABEL: vsel_double4:
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; SSSE3: # BB#0: # %entry
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; SSSE3-NEXT: movsd %xmm0, %xmm2
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; SSSE3-NEXT: movsd %xmm1, %xmm3
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; SSSE3-NEXT: movsd {{.*#+}} xmm2 = xmm0[0],xmm2[1]
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; SSSE3-NEXT: movsd {{.*#+}} xmm3 = xmm1[0],xmm3[1]
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; SSSE3-NEXT: movaps %xmm2, %xmm0
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; SSSE3-NEXT: movaps %xmm3, %xmm1
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; SSSE3-NEXT: retq
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@ -556,14 +556,14 @@ entry:
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define <4 x double> @constant_blendvpd_avx(<4 x double> %xy, <4 x double> %ab) {
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; SSE2-LABEL: constant_blendvpd_avx:
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; SSE2: # BB#0: # %entry
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; SSE2-NEXT: movsd %xmm1, %xmm3
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; SSE2-NEXT: movsd {{.*#+}} xmm3 = xmm1[0],xmm3[1]
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; SSE2-NEXT: movaps %xmm2, %xmm0
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; SSE2-NEXT: movaps %xmm3, %xmm1
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; SSE2-NEXT: retq
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;
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; SSSE3-LABEL: constant_blendvpd_avx:
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; SSSE3: # BB#0: # %entry
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; SSSE3-NEXT: movsd %xmm1, %xmm3
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; SSSE3-NEXT: movsd {{.*#+}} xmm3 = xmm1[0],xmm3[1]
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; SSSE3-NEXT: movaps %xmm2, %xmm0
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; SSSE3-NEXT: movaps %xmm3, %xmm1
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; SSSE3-NEXT: retq
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@ -709,7 +709,7 @@ entry:
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define <8 x float> @blend_shufflevector_8xfloat(<8 x float> %a, <8 x float> %b) {
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; SSE2-LABEL: blend_shufflevector_8xfloat:
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; SSE2: # BB#0: # %entry
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; SSE2-NEXT: movss %xmm0, %xmm2
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; SSE2-NEXT: movss {{.*#+}} xmm2 = xmm0[0],xmm2[1,2,3]
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; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm3[3,0]
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; SSE2-NEXT: shufps {{.*#+}} xmm3 = xmm3[0,1],xmm1[0,2]
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; SSE2-NEXT: movaps %xmm2, %xmm0
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@ -718,7 +718,7 @@ define <8 x float> @blend_shufflevector_8xfloat(<8 x float> %a, <8 x float> %b)
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;
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; SSSE3-LABEL: blend_shufflevector_8xfloat:
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; SSSE3: # BB#0: # %entry
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; SSSE3-NEXT: movss %xmm0, %xmm2
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; SSSE3-NEXT: movss {{.*#+}} xmm2 = xmm0[0],xmm2[1,2,3]
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; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm3[3,0]
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; SSSE3-NEXT: shufps {{.*#+}} xmm3 = xmm3[0,1],xmm1[0,2]
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; SSSE3-NEXT: movaps %xmm2, %xmm0
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@ -743,13 +743,13 @@ entry:
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define <4 x double> @blend_shufflevector_4xdouble(<4 x double> %a, <4 x double> %b) {
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; SSE2-LABEL: blend_shufflevector_4xdouble:
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; SSE2: # BB#0: # %entry
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; SSE2-NEXT: movsd %xmm0, %xmm2
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; SSE2-NEXT: movsd {{.*#+}} xmm2 = xmm0[0],xmm2[1]
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; SSE2-NEXT: movaps %xmm2, %xmm0
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; SSE2-NEXT: retq
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;
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; SSSE3-LABEL: blend_shufflevector_4xdouble:
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; SSSE3: # BB#0: # %entry
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; SSSE3-NEXT: movsd %xmm0, %xmm2
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; SSSE3-NEXT: movsd {{.*#+}} xmm2 = xmm0[0],xmm2[1]
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; SSSE3-NEXT: movaps %xmm2, %xmm0
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; SSSE3-NEXT: retq
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;
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@ -770,13 +770,13 @@ entry:
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define <4 x i64> @blend_shufflevector_4xi64(<4 x i64> %a, <4 x i64> %b) {
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; SSE2-LABEL: blend_shufflevector_4xi64:
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; SSE2: # BB#0: # %entry
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; SSE2-NEXT: movsd %xmm2, %xmm0
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; SSE2-NEXT: movsd {{.*#+}} xmm0 = xmm2[0],xmm0[1]
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; SSE2-NEXT: movaps %xmm3, %xmm1
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; SSE2-NEXT: retq
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;
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; SSSE3-LABEL: blend_shufflevector_4xi64:
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; SSSE3: # BB#0: # %entry
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; SSSE3-NEXT: movsd %xmm2, %xmm0
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; SSSE3-NEXT: movsd {{.*#+}} xmm0 = xmm2[0],xmm0[1]
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; SSSE3-NEXT: movaps %xmm3, %xmm1
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; SSSE3-NEXT: retq
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;
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@ -719,7 +719,7 @@ define <16 x i8> @shuffle_v16i8_zz_zz_19_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz(
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; AVX-LABEL: shuffle_v16i8_zz_zz_19_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz:
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; AVX: # BB#0:
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; AVX-NEXT: vmovd %edi, %xmm0
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; AVX-NEXT: vpslld $24, %xmm0
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; AVX-NEXT: vpslld $24, %xmm0, %xmm0
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; AVX-NEXT: vpshufb {{.*#+}} xmm0 = zero,zero,xmm0[3],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
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; AVX-NEXT: retq
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%a = insertelement <16 x i8> undef, i8 %i, i32 3
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@ -1197,7 +1197,7 @@ define <16 x i8> @shuffle_v16i8_zz_00_zz_02_zz_04_zz_06_zz_08_zz_10_zz_12_zz_14(
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;
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; AVX-LABEL: shuffle_v16i8_zz_00_zz_02_zz_04_zz_06_zz_08_zz_10_zz_12_zz_14:
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; AVX: # BB#0:
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; AVX-NEXT: vpsllw $8, %xmm0
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; AVX-NEXT: vpsllw $8, %xmm0, %xmm0
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; AVX-NEXT: retq
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%shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32><i32 16, i32 0, i32 16, i32 2, i32 16, i32 4, i32 16, i32 6, i32 16, i32 8, i32 16, i32 10, i32 16, i32 12, i32 16, i32 14>
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ret <16 x i8> %shuffle
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@ -1211,7 +1211,7 @@ define <16 x i8> @shuffle_v16i8_zz_zz_zz_00_zz_zz_zz_04_zz_zz_zz_08_zz_zz_zz_12(
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;
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; AVX-LABEL: shuffle_v16i8_zz_zz_zz_00_zz_zz_zz_04_zz_zz_zz_08_zz_zz_zz_12:
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; AVX: # BB#0:
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; AVX-NEXT: vpslld $24, %xmm0
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; AVX-NEXT: vpslld $24, %xmm0, %xmm0
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; AVX-NEXT: retq
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%shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32><i32 16, i32 16, i32 16, i32 0, i32 16, i32 16, i32 16, i32 4, i32 16, i32 16, i32 16, i32 8, i32 16, i32 16, i32 16, i32 12>
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ret <16 x i8> %shuffle
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@ -1225,7 +1225,7 @@ define <16 x i8> @shuffle_v16i8_zz_zz_zz_zz_zz_zz_zz_00_zz_zz_zz_zz_zz_zz_zz_08(
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;
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; AVX-LABEL: shuffle_v16i8_zz_zz_zz_zz_zz_zz_zz_00_zz_zz_zz_zz_zz_zz_zz_08:
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; AVX: # BB#0:
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; AVX-NEXT: vpsllq $56, %xmm0
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; AVX-NEXT: vpsllq $56, %xmm0, %xmm0
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; AVX-NEXT: retq
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%shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32><i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 0, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 8>
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ret <16 x i8> %shuffle
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@ -1239,7 +1239,7 @@ define <16 x i8> @shuffle_v16i8_zz_00_uu_02_03_uu_05_06_zz_08_09_uu_11_12_13_14(
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;
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; AVX-LABEL: shuffle_v16i8_zz_00_uu_02_03_uu_05_06_zz_08_09_uu_11_12_13_14:
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; AVX: # BB#0:
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; AVX-NEXT: vpsllq $8, %xmm0
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; AVX-NEXT: vpsllq $8, %xmm0, %xmm0
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; AVX-NEXT: retq
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%shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32><i32 16, i32 0, i32 undef, i32 2, i32 3, i32 undef, i32 5, i32 6, i32 16, i32 8, i32 9, i32 undef, i32 11, i32 12, i32 13, i32 14>
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ret <16 x i8> %shuffle
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@ -1253,7 +1253,7 @@ define <16 x i8> @shuffle_v16i8_01_uu_uu_uu_uu_zz_uu_zz_uu_zz_11_zz_13_zz_15_zz(
|
||||
;
|
||||
; AVX-LABEL: shuffle_v16i8_01_uu_uu_uu_uu_zz_uu_zz_uu_zz_11_zz_13_zz_15_zz:
|
||||
; AVX: # BB#0:
|
||||
; AVX-NEXT: vpsrlw $8, %xmm0
|
||||
; AVX-NEXT: vpsrlw $8, %xmm0, %xmm0
|
||||
; AVX-NEXT: retq
|
||||
%shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32><i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 16, i32 undef, i32 16, i32 undef, i32 16, i32 11, i32 16, i32 13, i32 16, i32 15, i32 16>
|
||||
ret <16 x i8> %shuffle
|
||||
@ -1267,7 +1267,7 @@ define <16 x i8> @shuffle_v16i8_02_03_zz_zz_06_07_uu_uu_uu_uu_uu_uu_14_15_zz_zz(
|
||||
;
|
||||
; AVX-LABEL: shuffle_v16i8_02_03_zz_zz_06_07_uu_uu_uu_uu_uu_uu_14_15_zz_zz:
|
||||
; AVX: # BB#0:
|
||||
; AVX-NEXT: vpsrld $16, %xmm0
|
||||
; AVX-NEXT: vpsrld $16, %xmm0, %xmm0
|
||||
; AVX-NEXT: retq
|
||||
%shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32><i32 2, i32 3, i32 16, i32 16, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 14, i32 15, i32 16, i32 16>
|
||||
ret <16 x i8> %shuffle
|
||||
@ -1281,7 +1281,7 @@ define <16 x i8> @shuffle_v16i8_07_zz_zz_zz_zz_zz_uu_uu_15_uu_uu_uu_uu_uu_zz_zz(
|
||||
;
|
||||
; AVX-LABEL: shuffle_v16i8_07_zz_zz_zz_zz_zz_uu_uu_15_uu_uu_uu_uu_uu_zz_zz:
|
||||
; AVX: # BB#0:
|
||||
; AVX-NEXT: vpsrlq $56, %xmm0
|
||||
; AVX-NEXT: vpsrlq $56, %xmm0, %xmm0
|
||||
; AVX-NEXT: retq
|
||||
%shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32><i32 7, i32 16, i32 16, i32 16, i32 16, i32 16, i32 undef, i32 undef, i32 15, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 16, i32 16>
|
||||
ret <16 x i8> %shuffle
|
||||
|
||||
@ -1091,22 +1091,22 @@ define <2 x double> @insert_dup_mem_v2f64(double* %ptr) {
|
||||
;
|
||||
; SSE3-LABEL: insert_dup_mem_v2f64:
|
||||
; SSE3: # BB#0:
|
||||
; SSE3-NEXT: movddup (%rdi), %xmm0
|
||||
; SSE3-NEXT: movddup {{.*#+}} xmm0 = mem[0,0]
|
||||
; SSE3-NEXT: retq
|
||||
;
|
||||
; SSSE3-LABEL: insert_dup_mem_v2f64:
|
||||
; SSSE3: # BB#0:
|
||||
; SSSE3-NEXT: movddup (%rdi), %xmm0
|
||||
; SSSE3-NEXT: movddup {{.*#+}} xmm0 = mem[0,0]
|
||||
; SSSE3-NEXT: retq
|
||||
;
|
||||
; SSE41-LABEL: insert_dup_mem_v2f64:
|
||||
; SSE41: # BB#0:
|
||||
; SSE41-NEXT: movddup (%rdi), %xmm0
|
||||
; SSE41-NEXT: movddup {{.*#+}} xmm0 = mem[0,0]
|
||||
; SSE41-NEXT: retq
|
||||
;
|
||||
; AVX-LABEL: insert_dup_mem_v2f64:
|
||||
; AVX: # BB#0:
|
||||
; AVX-NEXT: vmovddup (%rdi), %xmm0
|
||||
; AVX-NEXT: vmovddup {{.*#+}} xmm0 = mem[0,0]
|
||||
; AVX-NEXT: retq
|
||||
%a = load double* %ptr
|
||||
%v = insertelement <2 x double> undef, double %a, i32 0
|
||||
|
||||
@ -1383,7 +1383,7 @@ define <16 x i16> @shuffle_v16i16_zz_00_zz_02_zz_04_zz_06_zz_08_zz_10_zz_12_zz_1
|
||||
;
|
||||
; AVX2-LABEL: shuffle_v16i16_zz_00_zz_02_zz_04_zz_06_zz_08_zz_10_zz_12_zz_14:
|
||||
; AVX2: # BB#0:
|
||||
; AVX2-NEXT: vpslld $16, %ymm0
|
||||
; AVX2-NEXT: vpslld $16, %ymm0, %ymm0
|
||||
; AVX2-NEXT: retq
|
||||
%shuffle = shufflevector <16 x i16> %a, <16 x i16> zeroinitializer, <16 x i32> <i32 16, i32 0, i32 16, i32 2, i32 16, i32 4, i32 16, i32 6, i32 16, i32 8, i32 16, i32 10, i32 16, i32 12, i32 16, i32 14>
|
||||
ret <16 x i16> %shuffle
|
||||
@ -1410,7 +1410,7 @@ define <16 x i16> @shuffle_v16i16_zz_zz_zz_00_zz_zz_zz_04_zz_zz_zz_08_zz_zz_zz_1
|
||||
;
|
||||
; AVX2-LABEL: shuffle_v16i16_zz_zz_zz_00_zz_zz_zz_04_zz_zz_zz_08_zz_zz_zz_12:
|
||||
; AVX2: # BB#0:
|
||||
; AVX2-NEXT: vpsllq $48, %ymm0
|
||||
; AVX2-NEXT: vpsllq $48, %ymm0, %ymm0
|
||||
; AVX2-NEXT: retq
|
||||
%shuffle = shufflevector <16 x i16> %a, <16 x i16> zeroinitializer, <16 x i32> <i32 16, i32 16, i32 16, i32 0, i32 16, i32 16, i32 16, i32 4, i32 16, i32 16, i32 16, i32 8, i32 16, i32 16, i32 16, i32 12>
|
||||
ret <16 x i16> %shuffle
|
||||
@ -1432,7 +1432,7 @@ define <16 x i16> @shuffle_v16i16_01_zz_03_zz_05_zz_07_zz_09_zz_11_zz_13_zz_15_z
|
||||
;
|
||||
; AVX2-LABEL: shuffle_v16i16_01_zz_03_zz_05_zz_07_zz_09_zz_11_zz_13_zz_15_zz:
|
||||
; AVX2: # BB#0:
|
||||
; AVX2-NEXT: vpsrld $16, %ymm0
|
||||
; AVX2-NEXT: vpsrld $16, %ymm0, %ymm0
|
||||
; AVX2-NEXT: retq
|
||||
%shuffle = shufflevector <16 x i16> %a, <16 x i16> zeroinitializer, <16 x i32> <i32 1, i32 16, i32 3, i32 16, i32 5, i32 16, i32 7, i32 16, i32 9, i32 16, i32 11, i32 16, i32 13, i32 16, i32 15, i32 16>
|
||||
ret <16 x i16> %shuffle
|
||||
@ -1461,7 +1461,7 @@ define <16 x i16> @shuffle_v16i16_02_03_zz_zz_06_07_zz_zz_10_11_zz_zz_14_15_zz_z
|
||||
;
|
||||
; AVX2-LABEL: shuffle_v16i16_02_03_zz_zz_06_07_zz_zz_10_11_zz_zz_14_15_zz_zz:
|
||||
; AVX2: # BB#0:
|
||||
; AVX2-NEXT: vpsrlq $32, %ymm0
|
||||
; AVX2-NEXT: vpsrlq $32, %ymm0, %ymm0
|
||||
; AVX2-NEXT: retq
|
||||
%shuffle = shufflevector <16 x i16> %a, <16 x i16> zeroinitializer, <16 x i32> <i32 2, i32 3, i32 16, i32 16, i32 6, i32 7, i32 16, i32 16, i32 10, i32 11, i32 16, i32 16, i32 14, i32 15, i32 16, i32 16>
|
||||
ret <16 x i16> %shuffle
|
||||
|
||||
@ -1667,7 +1667,7 @@ define <32 x i8> @shuffle_v32i8_zz_00_zz_02_zz_04_zz_06_zz_08_zz_10_zz_12_zz_14_
|
||||
; AVX1-NEXT: vpshufb %xmm2, %xmm1, %xmm1
|
||||
; AVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3
|
||||
; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm3 = xmm3[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
|
||||
; AVX1-NEXT: vpshuflw $0, %xmm3, %xmm3 # xmm3 = xmm3[0,0,0,0,4,5,6,7]
|
||||
; AVX1-NEXT: vpshuflw {{.*#+}} xmm3 = xmm3[0,0,0,0,4,5,6,7]
|
||||
; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm1 = xmm3[0],xmm1[0],xmm3[1],xmm1[1],xmm3[2],xmm1[2],xmm3[3],xmm1[3],xmm3[4],xmm1[4],xmm3[5],xmm1[5],xmm3[6],xmm1[6],xmm3[7],xmm1[7]
|
||||
; AVX1-NEXT: vpshufb %xmm2, %xmm0, %xmm0
|
||||
; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm0 = xmm3[0],xmm0[0],xmm3[1],xmm0[1],xmm3[2],xmm0[2],xmm3[3],xmm0[3],xmm3[4],xmm0[4],xmm3[5],xmm0[5],xmm3[6],xmm0[6],xmm3[7],xmm0[7]
|
||||
@ -1676,7 +1676,7 @@ define <32 x i8> @shuffle_v32i8_zz_00_zz_02_zz_04_zz_06_zz_08_zz_10_zz_12_zz_14_
|
||||
;
|
||||
; AVX2-LABEL: shuffle_v32i8_zz_00_zz_02_zz_04_zz_06_zz_08_zz_10_zz_12_zz_14_zz_16_zz_18_zz_20_zz_22_zz_24_zz_26_zz_28_zz_30:
|
||||
; AVX2: # BB#0:
|
||||
; AVX2-NEXT: vpsllw $8, %ymm0
|
||||
; AVX2-NEXT: vpsllw $8, %ymm0, %ymm0
|
||||
; AVX2-NEXT: retq
|
||||
%shuffle = shufflevector <32 x i8> %a, <32 x i8> zeroinitializer, <32 x i32> <i32 32, i32 0, i32 32, i32 2, i32 32, i32 4, i32 32, i32 6, i32 32, i32 8, i32 32, i32 10, i32 32, i32 12, i32 32, i32 14, i32 32, i32 16, i32 32, i32 18, i32 32, i32 20, i32 32, i32 22, i32 32, i32 24, i32 32, i32 26, i32 32, i32 28, i32 32, i32 30>
|
||||
ret <32 x i8> %shuffle
|
||||
@ -1698,7 +1698,7 @@ define <32 x i8> @shuffle_v32i8_zz_zz_00_01_zz_zz_04_05_zz_zz_08_09_zz_zz_12_13_
|
||||
;
|
||||
; AVX2-LABEL: shuffle_v32i8_zz_zz_00_01_zz_zz_04_05_zz_zz_08_09_zz_zz_12_13_zz_zz_16_17_zz_zz_20_21_zz_zz_24_25_zz_zz_28_29:
|
||||
; AVX2: # BB#0:
|
||||
; AVX2-NEXT: vpslld $16, %ymm0
|
||||
; AVX2-NEXT: vpslld $16, %ymm0, %ymm0
|
||||
; AVX2-NEXT: retq
|
||||
%shuffle = shufflevector <32 x i8> %a, <32 x i8> zeroinitializer, <32 x i32> <i32 32, i32 32, i32 0, i32 1, i32 32, i32 32, i32 4, i32 5, i32 32, i32 32, i32 8, i32 9, i32 32, i32 32, i32 12, i32 13, i32 32, i32 32, i32 16, i32 17, i32 32, i32 32, i32 20, i32 21, i32 32, i32 32, i32 24, i32 25, i32 32, i32 32, i32 28, i32 29>
|
||||
ret <32 x i8> %shuffle
|
||||
@ -1720,7 +1720,7 @@ define <32 x i8> @shuffle_v32i8_zz_zz_zz_zz_zz_zz_00_01_zz_zz_zz_zz_zz_zz_08_09_
|
||||
;
|
||||
; AVX2-LABEL: shuffle_v32i8_zz_zz_zz_zz_zz_zz_00_01_zz_zz_zz_zz_zz_zz_08_09_zz_zz_zz_zz_zz_zz_16_17_zz_zz_zz_zz_zz_zz_24_25:
|
||||
; AVX2: # BB#0:
|
||||
; AVX2-NEXT: vpsllq $48, %ymm0
|
||||
; AVX2-NEXT: vpsllq $48, %ymm0, %ymm0
|
||||
; AVX2-NEXT: retq
|
||||
%shuffle = shufflevector <32 x i8> %a, <32 x i8> zeroinitializer, <32 x i32> <i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 0, i32 1, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 8, i32 9, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 16, i32 17, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 24, i32 25>
|
||||
ret <32 x i8> %shuffle
|
||||
@ -1734,7 +1734,7 @@ define <32 x i8> @shuffle_v32i8_01_zz_03_zz_05_zz_07_zz_09_zz_11_zz_13_zz_15_zz_
|
||||
; AVX1-NEXT: vpshufb %xmm2, %xmm1, %xmm1
|
||||
; AVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3
|
||||
; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm3 = xmm3[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
|
||||
; AVX1-NEXT: vpshuflw $0, %xmm3, %xmm3 # xmm3 = xmm3[0,0,0,0,4,5,6,7]
|
||||
; AVX1-NEXT: vpshuflw {{.*#+}} xmm3 = xmm3[0,0,0,0,4,5,6,7]
|
||||
; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm1 = xmm1[0],xmm3[0],xmm1[1],xmm3[1],xmm1[2],xmm3[2],xmm1[3],xmm3[3],xmm1[4],xmm3[4],xmm1[5],xmm3[5],xmm1[6],xmm3[6],xmm1[7],xmm3[7]
|
||||
; AVX1-NEXT: vpshufb %xmm2, %xmm0, %xmm0
|
||||
; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1],xmm0[2],xmm3[2],xmm0[3],xmm3[3],xmm0[4],xmm3[4],xmm0[5],xmm3[5],xmm0[6],xmm3[6],xmm0[7],xmm3[7]
|
||||
@ -1743,7 +1743,7 @@ define <32 x i8> @shuffle_v32i8_01_zz_03_zz_05_zz_07_zz_09_zz_11_zz_13_zz_15_zz_
|
||||
;
|
||||
; AVX2-LABEL: shuffle_v32i8_01_zz_03_zz_05_zz_07_zz_09_zz_11_zz_13_zz_15_zz_17_zz_19_zz_21_zz_23_zz_25_zz_27_zz_29_zz_31_zz:
|
||||
; AVX2: # BB#0:
|
||||
; AVX2-NEXT: vpsrlw $8, %ymm0
|
||||
; AVX2-NEXT: vpsrlw $8, %ymm0, %ymm0
|
||||
; AVX2-NEXT: retq
|
||||
%shuffle = shufflevector <32 x i8> %a, <32 x i8> zeroinitializer, <32 x i32> <i32 1, i32 32, i32 3, i32 32, i32 5, i32 32, i32 7, i32 32, i32 9, i32 32, i32 11, i32 32, i32 13, i32 32, i32 15, i32 32, i32 17, i32 32, i32 19, i32 32, i32 21, i32 32, i32 23, i32 32, i32 25, i32 32, i32 27, i32 32, i32 29, i32 32, i32 31, i32 32>
|
||||
ret <32 x i8> %shuffle
|
||||
@ -1765,7 +1765,7 @@ define <32 x i8> @shuffle_v32i8_02_03_zz_zz_06_07_zz_zz_10_11_zz_zz_14_15_zz_zz_
|
||||
;
|
||||
; AVX2-LABEL: shuffle_v32i8_02_03_zz_zz_06_07_zz_zz_10_11_zz_zz_14_15_zz_zz_18_19_zz_zz_22_23_zz_zz_26_27_zz_zz_30_31_zz_zz:
|
||||
; AVX2: # BB#0:
|
||||
; AVX2-NEXT: vpsrld $16, %ymm0
|
||||
; AVX2-NEXT: vpsrld $16, %ymm0, %ymm0
|
||||
; AVX2-NEXT: retq
|
||||
%shuffle = shufflevector <32 x i8> %a, <32 x i8> zeroinitializer, <32 x i32> <i32 2, i32 3, i32 32, i32 32, i32 6, i32 7, i32 32, i32 32, i32 10, i32 11, i32 32, i32 32, i32 14, i32 15, i32 32, i32 32, i32 18, i32 19, i32 32, i32 32, i32 22, i32 23, i32 32, i32 32, i32 26, i32 27, i32 32, i32 32, i32 30, i32 31, i32 32, i32 32>
|
||||
ret <32 x i8> %shuffle
|
||||
@ -1791,7 +1791,7 @@ define <32 x i8> @shuffle_v32i8_07_zz_zz_zz_zz_zz_zz_zz_15_zz_zz_zz_zz_z_zz_zz_2
|
||||
;
|
||||
; AVX2-LABEL: shuffle_v32i8_07_zz_zz_zz_zz_zz_zz_zz_15_zz_zz_zz_zz_z_zz_zz_23_zz_zz_zz_zz_zz_zz_zz_31_zz_zz_zz_zz_zz_zz_zz:
|
||||
; AVX2: # BB#0:
|
||||
; AVX2-NEXT: vpsrlq $56, %ymm0
|
||||
; AVX2-NEXT: vpsrlq $56, %ymm0, %ymm0
|
||||
; AVX2-NEXT: retq
|
||||
%shuffle = shufflevector <32 x i8> %a, <32 x i8> zeroinitializer, <32 x i32> <i32 7, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 15, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 23, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 31, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32>
|
||||
ret <32 x i8> %shuffle
|
||||
@ -1812,12 +1812,12 @@ define <32 x i8> @shuffle_v32i8_32_zz_zz_zz_zz_zz_zz_zz_33_zz_zz_zz_zz_zz_zz_zz_
|
||||
; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3],xmm0[4],xmm2[4],xmm0[5],xmm2[5],xmm0[6],xmm2[6],xmm0[7],xmm2[7]
|
||||
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
|
||||
; AVX1-NEXT: retq
|
||||
|
||||
;
|
||||
; AVX2-LABEL: shuffle_v32i8_32_zz_zz_zz_zz_zz_zz_zz_33_zz_zz_zz_zz_zz_zz_zz_34_zz_zz_zz_zz_zz_zz_zz_35_zz_zz_zz_zz_zz_zz_zz:
|
||||
; AVX2: # BB#0:
|
||||
; AVX2-NEXT: vpmovzxbq {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,zero,zero,zero,zero,xmm0[1],zero,zero,zero,zero,zero,zero,zero,xmm0[2],zero,zero,zero,zero,zero,zero,zero,xmm0[3],zero,zero,zero,zero,zero,zero,zero
|
||||
; AVX2-NEXT: retq
|
||||
|
||||
%shuffle = shufflevector <32 x i8> zeroinitializer, <32 x i8> %a, <32 x i32> <i32 32, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 33, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 34, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 35, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
|
||||
ret <32 x i8> %shuffle
|
||||
}
|
||||
|
||||
@ -749,21 +749,8 @@ define <4 x i64> @shuffle_v4i64_0415(<4 x i64> %a, <4 x i64> %b) {
|
||||
}
|
||||
|
||||
define <4 x i64> @stress_test1(<4 x i64> %a, <4 x i64> %b) {
|
||||
; AVX1-LABEL: stress_test1:
|
||||
; AVX1: # BB#0:
|
||||
; AVX1-NEXT: vperm2f128 {{.*#+}} ymm0 = ymm1[2,3,0,1]
|
||||
; AVX1-NEXT: vpermilpd {{.*#+}} ymm2 = ymm0[1,0,3,2]
|
||||
; AVX1-NEXT: vblendpd {{.*#+}} ymm1 = ymm2[0],ymm1[1],ymm2[2,3]
|
||||
; AVX1-NEXT: vpermilpd {{.*#+}} ymm0 = ymm0[1,1,3,2]
|
||||
; AVX1-NEXT: vunpckhpd {{.*#+}} ymm0 = ymm0[1],ymm1[1],ymm0[3],ymm1[3]
|
||||
; AVX1-NEXT: retq
|
||||
;
|
||||
; AVX2-LABEL: stress_test1:
|
||||
; AVX2: # BB#0:
|
||||
; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm1[3,1,1,0]
|
||||
; AVX2-NEXT: vpermq {{.*#+}} ymm1 = ymm1[3,3,1,3]
|
||||
; AVX2-NEXT: vpunpckhqdq {{.*#+}} ymm0 = ymm1[1],ymm0[1],ymm1[3],ymm0[3]
|
||||
; AVX2-NEXT: retq
|
||||
; ALL-LABEL: stress_test1:
|
||||
; ALL: retq
|
||||
%c = shufflevector <4 x i64> %b, <4 x i64> undef, <4 x i32> <i32 3, i32 1, i32 1, i32 0>
|
||||
%d = shufflevector <4 x i64> %c, <4 x i64> undef, <4 x i32> <i32 3, i32 undef, i32 2, i32 undef>
|
||||
%e = shufflevector <4 x i64> %b, <4 x i64> undef, <4 x i32> <i32 3, i32 3, i32 1, i32 undef>
|
||||
@ -847,7 +834,7 @@ define <4 x double> @splat_mem_v4f64(double* %ptr) {
|
||||
define <4 x i64> @splat_mem_v4i64(i64* %ptr) {
|
||||
; AVX1-LABEL: splat_mem_v4i64:
|
||||
; AVX1: # BB#0:
|
||||
; AVX1-NEXT: vmovddup (%rdi), %xmm0
|
||||
; AVX1-NEXT: vmovddup {{.*#+}} xmm0 = mem[0,0]
|
||||
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
|
||||
; AVX1-NEXT: retq
|
||||
;
|
||||
|
||||
@ -1862,7 +1862,7 @@ define <8 x i32> @shuffle_v8i32_z0U2zUz6(<8 x i32> %a) {
|
||||
;
|
||||
; AVX2-LABEL: shuffle_v8i32_z0U2zUz6:
|
||||
; AVX2: # BB#0:
|
||||
; AVX2-NEXT: vpsllq $32, %ymm0
|
||||
; AVX2-NEXT: vpsllq $32, %ymm0, %ymm0
|
||||
; AVX2-NEXT: retq
|
||||
%shuffle = shufflevector <8 x i32> %a, <8 x i32> zeroinitializer, <8 x i32> <i32 8, i32 0, i32 undef, i32 2, i32 8, i32 undef, i32 8, i32 6>
|
||||
ret <8 x i32> %shuffle
|
||||
@ -1878,7 +1878,7 @@ define <8 x i32> @shuffle_v8i32_1U3z5zUU(<8 x i32> %a) {
|
||||
;
|
||||
; AVX2-LABEL: shuffle_v8i32_1U3z5zUU:
|
||||
; AVX2: # BB#0:
|
||||
; AVX2-NEXT: vpsrlq $32, %ymm0
|
||||
; AVX2-NEXT: vpsrlq $32, %ymm0, %ymm0
|
||||
; AVX2-NEXT: retq
|
||||
%shuffle = shufflevector <8 x i32> %a, <8 x i32> zeroinitializer, <8 x i32> <i32 1, i32 undef, i32 3, i32 8, i32 5, i32 8, i32 undef, i32 undef>
|
||||
ret <8 x i32> %shuffle
|
||||
|
||||
@ -2,13 +2,13 @@
|
||||
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE41
|
||||
|
||||
define <4 x i32> @test1(<4 x i32> %A, <4 x i32> %B) {
|
||||
; SSE2-LABEL: test1
|
||||
; SSE2-LABEL: test1:
|
||||
; SSE2: # BB#0:
|
||||
; SSE2-NEXT: movsd %xmm0, %xmm1
|
||||
; SSE2-NEXT: movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1]
|
||||
; SSE2-NEXT: movaps %xmm1, %xmm0
|
||||
; SSE2-NEXT: retq
|
||||
;
|
||||
; SSE41-LABEL: test1
|
||||
; SSE41-LABEL: test1:
|
||||
; SSE41: # BB#0:
|
||||
; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
|
||||
; SSE41-NEXT: retq
|
||||
@ -17,12 +17,12 @@ define <4 x i32> @test1(<4 x i32> %A, <4 x i32> %B) {
|
||||
}
|
||||
|
||||
define <4 x i32> @test2(<4 x i32> %A, <4 x i32> %B) {
|
||||
; SSE2-LABEL: test2
|
||||
; SSE2-LABEL: test2:
|
||||
; SSE2: # BB#0:
|
||||
; SSE2-NEXT: movsd %xmm1, %xmm0
|
||||
; SSE2-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
|
||||
; SSE2-NEXT: retq
|
||||
;
|
||||
; SSE41-LABEL: test2
|
||||
; SSE41-LABEL: test2:
|
||||
; SSE41: # BB#0:
|
||||
; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7]
|
||||
; SSE41-NEXT: retq
|
||||
@ -31,13 +31,13 @@ define <4 x i32> @test2(<4 x i32> %A, <4 x i32> %B) {
|
||||
}
|
||||
|
||||
define <4 x float> @test3(<4 x float> %A, <4 x float> %B) {
|
||||
; SSE2-LABEL: test3
|
||||
; SSE2-LABEL: test3:
|
||||
; SSE2: # BB#0:
|
||||
; SSE2-NEXT: movsd %xmm0, %xmm1
|
||||
; SSE2-NEXT: movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1]
|
||||
; SSE2-NEXT: movaps %xmm1, %xmm0
|
||||
; SSE2-NEXT: retq
|
||||
;
|
||||
; SSE41-LABEL: test3
|
||||
; SSE41-LABEL: test3:
|
||||
; SSE41: # BB#0:
|
||||
; SSE41-NEXT: blendpd {{.*#+}} xmm0 = xmm0[0],xmm1[1]
|
||||
; SSE41-NEXT: retq
|
||||
@ -46,12 +46,12 @@ define <4 x float> @test3(<4 x float> %A, <4 x float> %B) {
|
||||
}
|
||||
|
||||
define <4 x float> @test4(<4 x float> %A, <4 x float> %B) {
|
||||
; SSE2-LABEL: test4
|
||||
; SSE2-LABEL: test4:
|
||||
; SSE2: # BB#0:
|
||||
; SSE2-NEXT: movsd %xmm1, %xmm0
|
||||
; SSE2-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
|
||||
; SSE2-NEXT: retq
|
||||
;
|
||||
; SSE41-LABEL: test4
|
||||
; SSE41-LABEL: test4:
|
||||
; SSE41: # BB#0:
|
||||
; SSE41-NEXT: blendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
|
||||
; SSE41-NEXT: retq
|
||||
|
||||
@ -17,7 +17,7 @@ define <4 x float> @test1(<4 x float> %a, <4 x float> %b) {
|
||||
define <4 x float> @test2(<4 x float> %a, <4 x float> %b) {
|
||||
; CHECK-LABEL: test2:
|
||||
; CHECK: # BB#0:
|
||||
; CHECK-NEXT: movsd %xmm0, %xmm1
|
||||
; CHECK-NEXT: movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1]
|
||||
; CHECK-NEXT: movaps %xmm1, %xmm0
|
||||
; CHECK-NEXT: retq
|
||||
%1 = select <4 x i1> <i1 true, i1 true, i1 false, i1 false>, <4 x float> %a, <4 x float> %b
|
||||
@ -27,7 +27,7 @@ define <4 x float> @test2(<4 x float> %a, <4 x float> %b) {
|
||||
define <4 x float> @test3(<4 x float> %a, <4 x float> %b) {
|
||||
; CHECK-LABEL: test3:
|
||||
; CHECK: # BB#0:
|
||||
; CHECK-NEXT: movsd %xmm1, %xmm0
|
||||
; CHECK-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
|
||||
; CHECK-NEXT: retq
|
||||
%1 = select <4 x i1> <i1 false, i1 false, i1 true, i1 true>, <4 x float> %a, <4 x float> %b
|
||||
ret <4 x float> %1
|
||||
@ -169,7 +169,7 @@ define <8 x i16> @test17(<8 x i16> %a, <8 x i16> %b) {
|
||||
define <4 x float> @test18(<4 x float> %a, <4 x float> %b) {
|
||||
; CHECK-LABEL: test18:
|
||||
; CHECK: # BB#0:
|
||||
; CHECK-NEXT: movss %xmm1, %xmm0
|
||||
; CHECK-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
|
||||
; CHECK-NEXT: retq
|
||||
%1 = select <4 x i1> <i1 false, i1 true, i1 true, i1 true>, <4 x float> %a, <4 x float> %b
|
||||
ret <4 x float> %1
|
||||
@ -178,7 +178,7 @@ define <4 x float> @test18(<4 x float> %a, <4 x float> %b) {
|
||||
define <4 x i32> @test19(<4 x i32> %a, <4 x i32> %b) {
|
||||
; CHECK-LABEL: test19:
|
||||
; CHECK: # BB#0:
|
||||
; CHECK-NEXT: movss %xmm1, %xmm0
|
||||
; CHECK-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
|
||||
; CHECK-NEXT: retq
|
||||
%1 = select <4 x i1> <i1 false, i1 true, i1 true, i1 true>, <4 x i32> %a, <4 x i32> %b
|
||||
ret <4 x i32> %1
|
||||
@ -187,7 +187,7 @@ define <4 x i32> @test19(<4 x i32> %a, <4 x i32> %b) {
|
||||
define <2 x double> @test20(<2 x double> %a, <2 x double> %b) {
|
||||
; CHECK-LABEL: test20:
|
||||
; CHECK: # BB#0:
|
||||
; CHECK-NEXT: movsd %xmm1, %xmm0
|
||||
; CHECK-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
|
||||
; CHECK-NEXT: retq
|
||||
%1 = select <2 x i1> <i1 false, i1 true>, <2 x double> %a, <2 x double> %b
|
||||
ret <2 x double> %1
|
||||
@ -196,7 +196,7 @@ define <2 x double> @test20(<2 x double> %a, <2 x double> %b) {
|
||||
define <2 x i64> @test21(<2 x i64> %a, <2 x i64> %b) {
|
||||
; CHECK-LABEL: test21:
|
||||
; CHECK: # BB#0:
|
||||
; CHECK-NEXT: movsd %xmm1, %xmm0
|
||||
; CHECK-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
|
||||
; CHECK-NEXT: retq
|
||||
%1 = select <2 x i1> <i1 false, i1 true>, <2 x i64> %a, <2 x i64> %b
|
||||
ret <2 x i64> %1
|
||||
@ -205,7 +205,7 @@ define <2 x i64> @test21(<2 x i64> %a, <2 x i64> %b) {
|
||||
define <4 x float> @test22(<4 x float> %a, <4 x float> %b) {
|
||||
; CHECK-LABEL: test22:
|
||||
; CHECK: # BB#0:
|
||||
; CHECK-NEXT: movss %xmm0, %xmm1
|
||||
; CHECK-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
|
||||
; CHECK-NEXT: movaps %xmm1, %xmm0
|
||||
; CHECK-NEXT: retq
|
||||
%1 = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x float> %a, <4 x float> %b
|
||||
@ -215,7 +215,7 @@ define <4 x float> @test22(<4 x float> %a, <4 x float> %b) {
|
||||
define <4 x i32> @test23(<4 x i32> %a, <4 x i32> %b) {
|
||||
; CHECK-LABEL: test23:
|
||||
; CHECK: # BB#0:
|
||||
; CHECK-NEXT: movss %xmm0, %xmm1
|
||||
; CHECK-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
|
||||
; CHECK-NEXT: movaps %xmm1, %xmm0
|
||||
; CHECK-NEXT: retq
|
||||
%1 = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x i32> %a, <4 x i32> %b
|
||||
@ -225,7 +225,7 @@ define <4 x i32> @test23(<4 x i32> %a, <4 x i32> %b) {
|
||||
define <2 x double> @test24(<2 x double> %a, <2 x double> %b) {
|
||||
; CHECK-LABEL: test24:
|
||||
; CHECK: # BB#0:
|
||||
; CHECK-NEXT: movsd %xmm0, %xmm1
|
||||
; CHECK-NEXT: movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1]
|
||||
; CHECK-NEXT: movaps %xmm1, %xmm0
|
||||
; CHECK-NEXT: retq
|
||||
%1 = select <2 x i1> <i1 true, i1 false>, <2 x double> %a, <2 x double> %b
|
||||
@ -235,7 +235,7 @@ define <2 x double> @test24(<2 x double> %a, <2 x double> %b) {
|
||||
define <2 x i64> @test25(<2 x i64> %a, <2 x i64> %b) {
|
||||
; CHECK-LABEL: test25:
|
||||
; CHECK: # BB#0:
|
||||
; CHECK-NEXT: movsd %xmm0, %xmm1
|
||||
; CHECK-NEXT: movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1]
|
||||
; CHECK-NEXT: movaps %xmm1, %xmm0
|
||||
; CHECK-NEXT: retq
|
||||
%1 = select <2 x i1> <i1 true, i1 false>, <2 x i64> %a, <2 x i64> %b
|
||||
|
||||
Loading…
Reference in New Issue
Block a user