mirror of
https://github.com/c64scene-ar/llvm-6502.git
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* Get rid of constant-expr handling code: we use the ConstantExpr lowering pass
* Use the SetCC handling code in the format of Brian's V8 * Add FIXMEs where calls to functions are being made without adding them to the Module first... they cause missing symbols at assembly-time. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14553 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Misha Brukman
parent
f233a84b3c
commit
425ff24bb3
@ -424,63 +424,6 @@ unsigned ISel::getFixedSizedAllocaFI(AllocaInst *AI) {
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void ISel::copyConstantToRegister(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator IP,
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Constant *C, unsigned R) {
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if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
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unsigned Class = 0;
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switch (CE->getOpcode()) {
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case Instruction::GetElementPtr:
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emitGEPOperation(MBB, IP, CE->getOperand(0),
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CE->op_begin()+1, CE->op_end(), R);
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return;
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case Instruction::Cast:
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emitCastOperation(MBB, IP, CE->getOperand(0), CE->getType(), R);
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return;
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case Instruction::Xor: ++Class; // FALL THROUGH
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case Instruction::Or: ++Class; // FALL THROUGH
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case Instruction::And: ++Class; // FALL THROUGH
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case Instruction::Sub: ++Class; // FALL THROUGH
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case Instruction::Add:
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emitSimpleBinaryOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
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Class, R);
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return;
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case Instruction::Mul:
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emitMultiply(MBB, IP, CE->getOperand(0), CE->getOperand(1), R);
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return;
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case Instruction::Div:
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case Instruction::Rem:
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emitDivRemOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
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CE->getOpcode() == Instruction::Div, R);
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return;
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case Instruction::SetNE:
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case Instruction::SetEQ:
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case Instruction::SetLT:
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case Instruction::SetGT:
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case Instruction::SetLE:
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case Instruction::SetGE:
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emitSetCCOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
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CE->getOpcode(), R);
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return;
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case Instruction::Shl:
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case Instruction::Shr:
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emitShiftOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
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CE->getOpcode() == Instruction::Shl, CE->getType(), R);
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return;
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case Instruction::Select:
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emitSelectOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
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CE->getOperand(2), R);
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return;
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default:
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std::cerr << "Offending expr: " << C << "\n";
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assert(0 && "Constant expression not yet handled!\n");
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}
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}
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if (C->getType()->isIntegral()) {
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unsigned Class = getClassB(C->getType());
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@ -852,15 +795,6 @@ unsigned ISel::EmitComparison(unsigned OpNum, Value *Op0, Value *Op1,
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//BuildMI(*MBB, IP, PPC32::CMPLI, 2, PPC32::CR0).addReg(FinalTmp).addImm(0);
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return OpNum;
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} else {
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// Emit a sequence of code which compares the high and low parts once
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// each, then uses a conditional move to handle the overflow case. For
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// example, a setlt for long would generate code like this:
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//
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// AL = lo(op1) < lo(op2) // Always unsigned comparison
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// BL = hi(op1) < hi(op2) // Signedness depends on operands
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// dest = hi(op1) == hi(op2) ? BL : AL;
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//
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// FIXME: Not Yet Implemented
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std::cerr << "EmitComparison unimplemented: Opnum >= 2\n";
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abort();
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@ -893,15 +827,6 @@ unsigned ISel::EmitComparison(unsigned OpNum, Value *Op0, Value *Op1,
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//BuildMI(*MBB, IP, PPC32::CMPLI, 2, PPC32::CR0).addReg(FinalTmp).addImm(0);
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break; // Allow the sete or setne to be generated from flags set by OR
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} else {
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// Emit a sequence of code which compares the high and low parts once
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// each, then uses a conditional move to handle the overflow case. For
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// example, a setlt for long would generate code like this:
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//
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// AL = lo(op1) < lo(op2) // Signedness depends on operands
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// BL = hi(op1) < hi(op2) // Always unsigned comparison
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// dest = hi(op1) == hi(op2) ? BL : AL;
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//
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// FIXME: Not Yet Implemented
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std::cerr << "EmitComparison (cLong) unimplemented: Opnum >= 2\n";
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abort();
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@ -911,35 +836,89 @@ unsigned ISel::EmitComparison(unsigned OpNum, Value *Op0, Value *Op1,
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return OpNum;
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}
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/// SetCC instructions - Here we just emit boilerplate code to set a byte-sized
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/// register, then move it to wherever the result should be.
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/// visitSetCondInst -
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///
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void ISel::visitSetCondInst(SetCondInst &I) {
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if (canFoldSetCCIntoBranchOrSelect(&I))
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return; // Fold this into a branch or select.
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unsigned Op0Reg = getReg(I.getOperand(0));
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unsigned Op1Reg = getReg(I.getOperand(1));
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unsigned DestReg = getReg(I);
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MachineBasicBlock::iterator MII = BB->end();
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emitSetCCOperation(BB, MII, I.getOperand(0), I.getOperand(1), I.getOpcode(),
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DestReg);
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const Type *Ty = I.getOperand (0)->getType();
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assert(getClass(Ty) < cLong && "can't setcc on longs or fp yet");
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// Compare the two values.
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BuildMI(BB, PPC32::CMPW, 2, PPC32::CR0).addReg(Op0Reg).addReg(Op1Reg);
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unsigned BranchIdx;
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switch (I.getOpcode()) {
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default: assert(0 && "Unknown setcc instruction!");
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case Instruction::SetEQ: BranchIdx = 0; break;
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case Instruction::SetNE: BranchIdx = 1; break;
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case Instruction::SetLT: BranchIdx = 2; break;
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case Instruction::SetGT: BranchIdx = 3; break;
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case Instruction::SetLE: BranchIdx = 4; break;
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case Instruction::SetGE: BranchIdx = 5; break;
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}
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static unsigned OpcodeTab[] = {
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PPC32::BEQ, PPC32::BNE, PPC32::BLT, PPC32::BGT, PPC32::BLE, PPC32::BGE
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};
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unsigned Opcode = OpcodeTab[BranchIdx];
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MachineBasicBlock *thisMBB = BB;
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const BasicBlock *LLVM_BB = BB->getBasicBlock();
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// thisMBB:
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// ...
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// cmpTY cr0, r1, r2
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// bCC copy1MBB
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// b copy0MBB
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// FIXME: we wouldn't need copy0MBB (we could fold it into thisMBB)
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// if we could insert other, non-terminator instructions after the
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// bCC. But MBB->getFirstTerminator() can't understand this.
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MachineBasicBlock *copy1MBB = new MachineBasicBlock(LLVM_BB);
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F->getBasicBlockList().push_back(copy1MBB);
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BuildMI(BB, Opcode, 2).addReg(PPC32::CR0).addMBB(copy1MBB);
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MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
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F->getBasicBlockList().push_back(copy0MBB);
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BuildMI(BB, PPC32::B, 1).addMBB(copy0MBB);
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// Update machine-CFG edges
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BB->addSuccessor(copy1MBB);
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BB->addSuccessor(copy0MBB);
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// copy0MBB:
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// %FalseValue = li 0
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// ba sinkMBB
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BB = copy0MBB;
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unsigned FalseValue = makeAnotherReg(I.getType());
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BuildMI(BB, PPC32::LI, 1, FalseValue).addZImm(0);
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MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
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F->getBasicBlockList().push_back(sinkMBB);
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BuildMI(BB, PPC32::B, 1).addMBB(sinkMBB);
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// Update machine-CFG edges
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BB->addSuccessor(sinkMBB);
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DEBUG(std::cerr << "thisMBB is at " << (void*)thisMBB << "\n");
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DEBUG(std::cerr << "copy1MBB is at " << (void*)copy1MBB << "\n");
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DEBUG(std::cerr << "copy0MBB is at " << (void*)copy0MBB << "\n");
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DEBUG(std::cerr << "sinkMBB is at " << (void*)sinkMBB << "\n");
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// copy1MBB:
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// %TrueValue = li 1
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// ba sinkMBB
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BB = copy1MBB;
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unsigned TrueValue = makeAnotherReg (I.getType ());
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BuildMI(BB, PPC32::LI, 1, TrueValue).addZImm(1);
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BuildMI(BB, PPC32::B, 1).addMBB(sinkMBB);
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// Update machine-CFG edges
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BB->addSuccessor(sinkMBB);
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// sinkMBB:
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// %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, copy1MBB ]
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// ...
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BB = sinkMBB;
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BuildMI(BB, PPC32::PHI, 4, DestReg).addReg(FalseValue)
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.addMBB(copy0MBB).addReg(TrueValue).addMBB(copy1MBB);
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}
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/// emitSetCCOperation - Common code shared between visitSetCondInst and
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/// constant expression support.
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///
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/// FIXME: this is wrong. we should figure out a way to guarantee
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/// TargetReg is a CR and then make it a no-op
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void ISel::emitSetCCOperation(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator IP,
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Value *Op0, Value *Op1, unsigned Opcode,
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unsigned TargetReg) {
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unsigned OpNum = getSetCCNumber(Opcode);
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OpNum = EmitComparison(OpNum, Op0, Op1, MBB, IP);
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// The value is already in CR0 at this point, do nothing.
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}
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void ISel::visitSelectInst(SelectInst &SI) {
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unsigned DestReg = getReg(SI);
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MachineBasicBlock::iterator MII = BB->end();
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@ -1930,6 +1909,8 @@ void ISel::emitDivRemOperation(MachineBasicBlock *BB,
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} else { // Floating point remainder...
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unsigned Op0Reg = getReg(Op0, BB, IP);
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unsigned Op1Reg = getReg(Op1, BB, IP);
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// FIXME: Make sure the module has external function
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// double fmod(double, double)
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MachineInstr *TheCall =
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BuildMI(PPC32::CALLpcrel, 1).addExternalSymbol("fmod", true);
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std::vector<ValueRecord> Args;
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@ -1939,7 +1920,8 @@ void ISel::emitDivRemOperation(MachineBasicBlock *BB,
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}
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return;
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case cLong: {
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static const char *FnName[] =
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// FIXME: Make sure the module has external function
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static const char *FnName[] =
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{ "__moddi3", "__divdi3", "__umoddi3", "__udivdi3" };
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unsigned Op0Reg = getReg(Op0, BB, IP);
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unsigned Op1Reg = getReg(Op1, BB, IP);
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@ -424,63 +424,6 @@ unsigned ISel::getFixedSizedAllocaFI(AllocaInst *AI) {
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void ISel::copyConstantToRegister(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator IP,
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Constant *C, unsigned R) {
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if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
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unsigned Class = 0;
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switch (CE->getOpcode()) {
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case Instruction::GetElementPtr:
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emitGEPOperation(MBB, IP, CE->getOperand(0),
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CE->op_begin()+1, CE->op_end(), R);
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return;
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case Instruction::Cast:
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emitCastOperation(MBB, IP, CE->getOperand(0), CE->getType(), R);
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return;
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case Instruction::Xor: ++Class; // FALL THROUGH
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case Instruction::Or: ++Class; // FALL THROUGH
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case Instruction::And: ++Class; // FALL THROUGH
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case Instruction::Sub: ++Class; // FALL THROUGH
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case Instruction::Add:
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emitSimpleBinaryOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
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Class, R);
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return;
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case Instruction::Mul:
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emitMultiply(MBB, IP, CE->getOperand(0), CE->getOperand(1), R);
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return;
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case Instruction::Div:
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case Instruction::Rem:
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emitDivRemOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
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CE->getOpcode() == Instruction::Div, R);
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return;
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case Instruction::SetNE:
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case Instruction::SetEQ:
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case Instruction::SetLT:
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case Instruction::SetGT:
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case Instruction::SetLE:
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case Instruction::SetGE:
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emitSetCCOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
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CE->getOpcode(), R);
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return;
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case Instruction::Shl:
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case Instruction::Shr:
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emitShiftOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
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CE->getOpcode() == Instruction::Shl, CE->getType(), R);
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return;
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case Instruction::Select:
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emitSelectOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
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CE->getOperand(2), R);
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return;
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default:
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std::cerr << "Offending expr: " << C << "\n";
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assert(0 && "Constant expression not yet handled!\n");
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}
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}
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if (C->getType()->isIntegral()) {
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unsigned Class = getClassB(C->getType());
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@ -852,15 +795,6 @@ unsigned ISel::EmitComparison(unsigned OpNum, Value *Op0, Value *Op1,
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//BuildMI(*MBB, IP, PPC32::CMPLI, 2, PPC32::CR0).addReg(FinalTmp).addImm(0);
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return OpNum;
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} else {
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// Emit a sequence of code which compares the high and low parts once
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// each, then uses a conditional move to handle the overflow case. For
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// example, a setlt for long would generate code like this:
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//
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// AL = lo(op1) < lo(op2) // Always unsigned comparison
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// BL = hi(op1) < hi(op2) // Signedness depends on operands
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// dest = hi(op1) == hi(op2) ? BL : AL;
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//
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// FIXME: Not Yet Implemented
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std::cerr << "EmitComparison unimplemented: Opnum >= 2\n";
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abort();
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@ -893,15 +827,6 @@ unsigned ISel::EmitComparison(unsigned OpNum, Value *Op0, Value *Op1,
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//BuildMI(*MBB, IP, PPC32::CMPLI, 2, PPC32::CR0).addReg(FinalTmp).addImm(0);
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break; // Allow the sete or setne to be generated from flags set by OR
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} else {
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// Emit a sequence of code which compares the high and low parts once
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// each, then uses a conditional move to handle the overflow case. For
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// example, a setlt for long would generate code like this:
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//
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// AL = lo(op1) < lo(op2) // Signedness depends on operands
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// BL = hi(op1) < hi(op2) // Always unsigned comparison
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// dest = hi(op1) == hi(op2) ? BL : AL;
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//
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// FIXME: Not Yet Implemented
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std::cerr << "EmitComparison (cLong) unimplemented: Opnum >= 2\n";
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abort();
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@ -911,35 +836,89 @@ unsigned ISel::EmitComparison(unsigned OpNum, Value *Op0, Value *Op1,
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return OpNum;
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}
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/// SetCC instructions - Here we just emit boilerplate code to set a byte-sized
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/// register, then move it to wherever the result should be.
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/// visitSetCondInst -
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///
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void ISel::visitSetCondInst(SetCondInst &I) {
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if (canFoldSetCCIntoBranchOrSelect(&I))
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return; // Fold this into a branch or select.
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unsigned Op0Reg = getReg(I.getOperand(0));
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unsigned Op1Reg = getReg(I.getOperand(1));
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unsigned DestReg = getReg(I);
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MachineBasicBlock::iterator MII = BB->end();
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emitSetCCOperation(BB, MII, I.getOperand(0), I.getOperand(1), I.getOpcode(),
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DestReg);
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const Type *Ty = I.getOperand (0)->getType();
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assert(getClass(Ty) < cLong && "can't setcc on longs or fp yet");
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// Compare the two values.
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BuildMI(BB, PPC32::CMPW, 2, PPC32::CR0).addReg(Op0Reg).addReg(Op1Reg);
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unsigned BranchIdx;
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switch (I.getOpcode()) {
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default: assert(0 && "Unknown setcc instruction!");
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case Instruction::SetEQ: BranchIdx = 0; break;
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case Instruction::SetNE: BranchIdx = 1; break;
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case Instruction::SetLT: BranchIdx = 2; break;
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case Instruction::SetGT: BranchIdx = 3; break;
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case Instruction::SetLE: BranchIdx = 4; break;
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case Instruction::SetGE: BranchIdx = 5; break;
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}
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static unsigned OpcodeTab[] = {
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PPC32::BEQ, PPC32::BNE, PPC32::BLT, PPC32::BGT, PPC32::BLE, PPC32::BGE
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};
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unsigned Opcode = OpcodeTab[BranchIdx];
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MachineBasicBlock *thisMBB = BB;
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const BasicBlock *LLVM_BB = BB->getBasicBlock();
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// thisMBB:
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// ...
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// cmpTY cr0, r1, r2
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// bCC copy1MBB
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// b copy0MBB
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// FIXME: we wouldn't need copy0MBB (we could fold it into thisMBB)
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// if we could insert other, non-terminator instructions after the
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// bCC. But MBB->getFirstTerminator() can't understand this.
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MachineBasicBlock *copy1MBB = new MachineBasicBlock(LLVM_BB);
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F->getBasicBlockList().push_back(copy1MBB);
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BuildMI(BB, Opcode, 2).addReg(PPC32::CR0).addMBB(copy1MBB);
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MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
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F->getBasicBlockList().push_back(copy0MBB);
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BuildMI(BB, PPC32::B, 1).addMBB(copy0MBB);
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// Update machine-CFG edges
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BB->addSuccessor(copy1MBB);
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BB->addSuccessor(copy0MBB);
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// copy0MBB:
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// %FalseValue = li 0
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// ba sinkMBB
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BB = copy0MBB;
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unsigned FalseValue = makeAnotherReg(I.getType());
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BuildMI(BB, PPC32::LI, 1, FalseValue).addZImm(0);
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MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
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F->getBasicBlockList().push_back(sinkMBB);
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BuildMI(BB, PPC32::B, 1).addMBB(sinkMBB);
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// Update machine-CFG edges
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BB->addSuccessor(sinkMBB);
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DEBUG(std::cerr << "thisMBB is at " << (void*)thisMBB << "\n");
|
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DEBUG(std::cerr << "copy1MBB is at " << (void*)copy1MBB << "\n");
|
||||
DEBUG(std::cerr << "copy0MBB is at " << (void*)copy0MBB << "\n");
|
||||
DEBUG(std::cerr << "sinkMBB is at " << (void*)sinkMBB << "\n");
|
||||
|
||||
// copy1MBB:
|
||||
// %TrueValue = li 1
|
||||
// ba sinkMBB
|
||||
BB = copy1MBB;
|
||||
unsigned TrueValue = makeAnotherReg (I.getType ());
|
||||
BuildMI(BB, PPC32::LI, 1, TrueValue).addZImm(1);
|
||||
BuildMI(BB, PPC32::B, 1).addMBB(sinkMBB);
|
||||
// Update machine-CFG edges
|
||||
BB->addSuccessor(sinkMBB);
|
||||
|
||||
// sinkMBB:
|
||||
// %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, copy1MBB ]
|
||||
// ...
|
||||
BB = sinkMBB;
|
||||
BuildMI(BB, PPC32::PHI, 4, DestReg).addReg(FalseValue)
|
||||
.addMBB(copy0MBB).addReg(TrueValue).addMBB(copy1MBB);
|
||||
}
|
||||
|
||||
/// emitSetCCOperation - Common code shared between visitSetCondInst and
|
||||
/// constant expression support.
|
||||
///
|
||||
/// FIXME: this is wrong. we should figure out a way to guarantee
|
||||
/// TargetReg is a CR and then make it a no-op
|
||||
void ISel::emitSetCCOperation(MachineBasicBlock *MBB,
|
||||
MachineBasicBlock::iterator IP,
|
||||
Value *Op0, Value *Op1, unsigned Opcode,
|
||||
unsigned TargetReg) {
|
||||
unsigned OpNum = getSetCCNumber(Opcode);
|
||||
OpNum = EmitComparison(OpNum, Op0, Op1, MBB, IP);
|
||||
|
||||
// The value is already in CR0 at this point, do nothing.
|
||||
}
|
||||
|
||||
|
||||
void ISel::visitSelectInst(SelectInst &SI) {
|
||||
unsigned DestReg = getReg(SI);
|
||||
MachineBasicBlock::iterator MII = BB->end();
|
||||
@ -1930,6 +1909,8 @@ void ISel::emitDivRemOperation(MachineBasicBlock *BB,
|
||||
} else { // Floating point remainder...
|
||||
unsigned Op0Reg = getReg(Op0, BB, IP);
|
||||
unsigned Op1Reg = getReg(Op1, BB, IP);
|
||||
// FIXME: Make sure the module has external function
|
||||
// double fmod(double, double)
|
||||
MachineInstr *TheCall =
|
||||
BuildMI(PPC32::CALLpcrel, 1).addExternalSymbol("fmod", true);
|
||||
std::vector<ValueRecord> Args;
|
||||
@ -1939,7 +1920,8 @@ void ISel::emitDivRemOperation(MachineBasicBlock *BB,
|
||||
}
|
||||
return;
|
||||
case cLong: {
|
||||
static const char *FnName[] =
|
||||
// FIXME: Make sure the module has external function
|
||||
static const char *FnName[] =
|
||||
{ "__moddi3", "__divdi3", "__umoddi3", "__udivdi3" };
|
||||
unsigned Op0Reg = getReg(Op0, BB, IP);
|
||||
unsigned Op1Reg = getReg(Op1, BB, IP);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user