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Fix a regression from r147481. This combine should only happen if there is a
single use. rdar://11360370 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156316 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -13050,6 +13050,7 @@ static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
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// If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
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// If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
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if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
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if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
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if (Ld->hasNUsesOfValue(1, 0)) {
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SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
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SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
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SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
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SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
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SDValue ResNode =
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SDValue ResNode =
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@ -13061,6 +13062,7 @@ static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
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false/*WriteMem*/);
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false/*WriteMem*/);
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return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
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return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
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}
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}
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}
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// Emit a zeroed vector and insert the desired subvector on its
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// Emit a zeroed vector and insert the desired subvector on its
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// first half.
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// first half.
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@ -5,7 +5,8 @@
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; It's hard to test for the ISEL condition because CodeGen optimizes
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; It's hard to test for the ISEL condition because CodeGen optimizes
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; away the bugpointed code. Just ensure the basics are still there.
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; away the bugpointed code. Just ensure the basics are still there.
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;CHECK: func:
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;CHECK: func:
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;CHECK: vmovups
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;CHECK: vpxor
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;CHECK: vinsertf128
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;CHECK: vpshufd
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;CHECK: vpshufd
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;CHECK: vpshufd
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;CHECK: vpshufd
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;CHECK: vmulps
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;CHECK: vmulps
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