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Remove 2 unused multiclasses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171338 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -3101,32 +3101,6 @@ let Predicates = [HasAVX] in {
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[(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))], itins.rm>;
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}
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/// sse2_fp_unop_p_int - SSE2 intrinsic unops in vector forms.
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multiclass sse2_fp_unop_p_int<bits<8> opc, string OpcodeStr,
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Intrinsic V2F64Int, OpndItins itins> {
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def PDr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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!strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
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[(set VR128:$dst, (V2F64Int VR128:$src))],
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itins.rr>;
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def PDm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
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!strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
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[(set VR128:$dst, (V2F64Int (memopv2f64 addr:$src)))],
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itins.rm>;
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}
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/// sse2_fp_unop_p_y_int - AVX 256-bit intrinsic unops in vector forms.
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multiclass sse2_fp_unop_p_y_int<bits<8> opc, string OpcodeStr,
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Intrinsic V2F64Int, OpndItins itins> {
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def PDYr_Int : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
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!strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
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[(set VR256:$dst, (V2F64Int VR256:$src))],
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itins.rr>, VEX_L;
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def PDYm_Int : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
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!strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
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[(set VR256:$dst, (V2F64Int (memopv4f64 addr:$src)))],
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itins.rm>, VEX_L;
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}
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defm SQRT : sse1_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTP>,
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sse2_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTP>;
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defm RSQRT : sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt, SSE_SQRTP>;
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