6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-07-25 13:24:46 +00:00
Code Issues Projects Releases Wiki Activity

[ARM64] Fix disassembly logic for extended loads/stores with 32-bit registers.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205893 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bradley Smith
2014-04-09 14:44:36 +00:00
parent 6a82fbc29f
commit 42c672649c
2 changed files with 9 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp
View File

@@ -1368,10 +1368,10 @@ static DecodeStatus DecodeRegOffsetLdStInstruction(llvm::MCInst &Inst,
DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
if (extendHi == 0x3)
if ((extendHi & 0x3) == 0x3)
DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
else
DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
Inst.addOperand(MCOperand::CreateImm(extend));
return Success;