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[ARM64] Fix disassembly logic for extended loads/stores with 32-bit registers.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205893 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bradley Smith
2014-04-09 14:44:36 +00:00
parent 6a82fbc29f
commit 42c672649c
2 changed files with 9 additions and 5 deletions
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4
lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp
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@@ -1368,10 +1368,10 @@ static DecodeStatus DecodeRegOffsetLdStInstruction(llvm::MCInst &Inst,
DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
if (extendHi == 0x3)
if ((extendHi & 0x3) == 0x3)
DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
else
DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
Inst.addOperand(MCOperand::CreateImm(extend));
return Success;