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[ARM64] Fix disassembly logic for extended loads/stores with 32-bit registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205893 91177308-0d34-0410-b5e6-96231b3b80d8
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@@ -1368,10 +1368,10 @@ static DecodeStatus DecodeRegOffsetLdStInstruction(llvm::MCInst &Inst,
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DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
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if (extendHi == 0x3)
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if ((extendHi & 0x3) == 0x3)
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DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
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else
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DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
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DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
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Inst.addOperand(MCOperand::CreateImm(extend));
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return Success;
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