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[ARM64] Fix disassembly logic for extended loads/stores with 32-bit registers.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205893 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bradley Smith 2014-04-09 14:44:36 +00:00
parent 6a82fbc29f
commit 42c672649c
2 changed files with 9 additions and 5 deletions
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4
lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp
View File

@ -1368,10 +1368,10 @@ static DecodeStatus DecodeRegOffsetLdStInstruction(llvm::MCInst &Inst,
DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
if (extendHi == 0x3) if ((extendHi & 0x3) == 0x3)
DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
else else
DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
Inst.addOperand(MCOperand::CreateImm(extend)); Inst.addOperand(MCOperand::CreateImm(extend));
return Success; return Success;

10
test/MC/Disassembler/ARM64/memory.txt
View File

@ -83,6 +83,8 @@
0x64 0x00 0x00 0x39 0x64 0x00 0x00 0x39
0x85 0x50 0x00 0x39 0x85 0x50 0x00 0x39
0xe2 0x43 0x00 0x79 0xe2 0x43 0x00 0x79
0x00 0xe8 0x20 0x38
0x00 0x48 0x20 0x38
# CHECK: str x4, [x3] # CHECK: str x4, [x3]
# CHECK: str x2, [sp, #32] # CHECK: str x2, [sp, #32]
@ -95,6 +97,8 @@
# CHECK: strb w4, [x3] # CHECK: strb w4, [x3]
# CHECK: strb w5, [x4, #20] # CHECK: strb w5, [x4, #20]
# CHECK: strh w2, [sp, #32] # CHECK: strh w2, [sp, #32]
# CHECK: strb w0, [x0, x0, sxtx]
# CHECK: strb w0, [x0, w0, uxtw]
#----------------------------------------------------------------------------- #-----------------------------------------------------------------------------
# Unscaled immediate loads and stores # Unscaled immediate loads and stores
@ -422,11 +426,11 @@
0xe1 0x6b 0xa3 0x3c 0xe1 0x6b 0xa3 0x3c
0xe1 0x5b 0xa3 0x3c 0xe1 0x5b 0xa3 0x3c
# CHECK: str h0, [x0, x0, uxtw] # CHECK: str h0, [x0, w0, uxtw]
# CHECK: str d1, [sp, x3] # CHECK: str d1, [sp, x3]
# CHECK: str d1, [sp, x3, uxtw #3] # CHECK: str d1, [sp, w3, uxtw #3]
# CHECK: str q1, [sp, x3] # CHECK: str q1, [sp, x3]
# CHECK: str q1, [sp, x3, uxtw #4] # CHECK: str q1, [sp, w3, uxtw #4]
#----------------------------------------------------------------------------- #-----------------------------------------------------------------------------
# Load/Store exclusive # Load/Store exclusive