mirror of
https://github.com/c64scene-ar/llvm-6502.git
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Reverted AVX-512 vector shuffle
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240258 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Elena Demikhovsky
parent
12219f8c85
commit
42ceb12123
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@ -6259,42 +6259,6 @@ is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
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return true;
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}
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/// \brief Test whether a shuffle mask is equivalent within each 256-bit lane.
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///
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/// This checks a shuffle mask to see if it is performing the same
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/// 256-bit lane-relative shuffle in each 256-bit lane. This trivially implies
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/// that it is also not lane-crossing. It may however involve a blend from the
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/// same lane of a second vector.
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///
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/// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
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/// non-trivial to compute in the face of undef lanes. The representation is
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/// *not* suitable for use with existing 256-bit shuffles as it will contain
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/// entries from both V1 and V2 inputs to the wider mask.
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static bool
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is256BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
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SmallVectorImpl<int> &RepeatedMask) {
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int LaneSize = 256 / VT.getScalarSizeInBits();
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RepeatedMask.resize(LaneSize, -1);
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int Size = Mask.size();
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for (int i = 0; i < Size; ++i) {
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if (Mask[i] < 0)
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continue;
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if ((Mask[i] % Size) / LaneSize != i / LaneSize)
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// This entry crosses lanes, so there is no way to model this shuffle.
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return false;
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// Ok, handle the in-lane shuffles by detecting if and when they repeat.
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if (RepeatedMask[i % LaneSize] == -1)
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// This is the first non-undef entry in this slot of a 256-bit lane.
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RepeatedMask[i % LaneSize] =
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Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
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else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
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// Found a mismatch with the repeated mask.
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return false;
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}
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return true;
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}
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/// \brief Checks whether a shuffle mask is equivalent to an explicit list of
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/// arguments.
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///
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@ -6354,22 +6318,6 @@ static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask, SDLoc DL,
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return DAG.getConstant(Imm, DL, MVT::i8);
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}
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/// \brief Get a 8-bit shuffle, 1 bit per lane, immediate for a mask.
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///
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/// This helper function produces an 8-bit shuffle immediate corresponding to
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/// the ubiquitous shuffle encoding scheme used in x86 instructions for
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/// shuffling 8 lanes.
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static SDValue get1bitLaneShuffleImm8ForMask(ArrayRef<int> Mask, SDLoc DL,
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SelectionDAG &DAG) {
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assert(Mask.size() <= 8 &&
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"Up to 8 elts may be in Imm8 1-bit lane shuffle mask");
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unsigned Imm = 0;
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for (unsigned i = 0; i < Mask.size(); ++i)
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if (Mask[i] >= 0)
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Imm |= (Mask[i] % 2) << i;
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return DAG.getConstant(Imm, DL, MVT::i8);
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}
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/// \brief Try to emit a blend instruction for a shuffle using bit math.
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///
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/// This is used as a fallback approach when first class blend instructions are
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@ -9385,30 +9333,6 @@ static SDValue lowerV2X128VectorShuffle(SDLoc DL, MVT VT, SDValue V1,
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DAG.getConstant(PermMask, DL, MVT::i8));
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}
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/// \brief Handle lowering 4-lane 128-bit shuffles.
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static SDValue lowerV4X128VectorShuffle(SDLoc DL, MVT VT, SDValue V1,
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SDValue V2, ArrayRef<int> WidenedMask,
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SelectionDAG &DAG) {
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assert(WidenedMask.size() == 4 && "Unexpected mask size for 128bit shuffle!");
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// form a 128-bit permutation.
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// convert the 64-bit shuffle mask selection values into 128-bit selection
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// bits defined by a vshuf64x2 instruction's immediate control byte.
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unsigned PermMask = 0, Imm = 0;
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for (int i = 0, Size = WidenedMask.size(); i < Size; ++i) {
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if(WidenedMask[i] == SM_SentinelZero)
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return SDValue();
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// use first element in place of undef musk
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Imm = (WidenedMask[i] == SM_SentinelUndef) ? 0 : WidenedMask[i];
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PermMask |= (Imm % 4) << (i * 2);
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}
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return DAG.getNode(X86ISD::SHUF128, DL, VT, V1, V2,
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DAG.getConstant(PermMask, DL, MVT::i8));
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}
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/// \brief Lower a vector shuffle by first fixing the 128-bit lanes and then
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/// shuffling each lane.
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///
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@ -10144,105 +10068,35 @@ static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
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}
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}
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static SDValue lowerVectorShuffleWithVALIGN(SDLoc DL, MVT VT,
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ArrayRef<int> Mask, SDValue V1,
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SDValue V2, SelectionDAG &DAG) {
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assert(VT.getScalarSizeInBits() >= 32 && "Unexpected data type for VALIGN");
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// VALIGN pattern 2, 3, 4, 5, .. (sequential, shifted right)
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int AlignVal = -1;
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for (int i = 0; i < (signed)VT.getVectorNumElements(); ++i) {
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if (Mask[i] < 0)
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continue;
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if (Mask[i] < i)
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return SDValue();
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if (AlignVal == -1)
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AlignVal = Mask[i] - i;
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else if (Mask[i] - i != AlignVal)
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return SDValue();
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}
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// Vector source operands should be swapped
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return DAG.getNode(X86ISD::VALIGN, DL, VT, V2, V1,
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DAG.getConstant(AlignVal, DL, MVT::i8));
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}
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static SDValue lowerVectorShuffleWithPERMV(SDLoc DL, MVT VT,
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ArrayRef<int> Mask, SDValue V1,
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SDValue V2, SelectionDAG &DAG) {
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assert(VT.getScalarSizeInBits() >= 16 && "Unexpected data type for PERMV");
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MVT MaskEltVT = MVT::getIntegerVT(VT.getScalarSizeInBits());
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MVT MaskVecVT = MVT::getVectorVT(MaskEltVT, VT.getVectorNumElements());
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SmallVector<SDValue, 32> VPermMask;
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for (unsigned i = 0; i < VT.getVectorNumElements(); ++i)
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VPermMask.push_back(Mask[i] < 0 ? DAG.getUNDEF(MaskEltVT) :
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DAG.getConstant(Mask[i], DL,MaskEltVT));
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SDValue MaskNode = DAG.getNode(ISD::BUILD_VECTOR, DL, MaskVecVT,
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VPermMask);
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if (isSingleInputShuffleMask(Mask))
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return DAG.getNode(X86ISD::VPERMV, DL, VT, MaskNode, V1);
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return DAG.getNode(X86ISD::VPERMV3, DL, VT, MaskNode, V1, V2);
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}
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/// \brief Handle lowering of 8-lane 64-bit floating point shuffles.
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static SDValue lowerV8X64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
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static SDValue lowerV8F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
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const X86Subtarget *Subtarget,
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SelectionDAG &DAG) {
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SDLoc DL(Op);
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MVT VT = Op.getSimpleValueType();
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assert((V1.getSimpleValueType() == MVT::v8f64 ||
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V1.getSimpleValueType() == MVT::v8i64) && "Bad operand type!");
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assert((V2.getSimpleValueType() == MVT::v8f64 ||
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V2.getSimpleValueType() == MVT::v8i64) && "Bad operand type!");
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assert(V1.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
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assert(V2.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
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ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
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ArrayRef<int> Mask = SVOp->getMask();
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assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
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SmallVector<int, 4> WidenedMask;
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if (canWidenShuffleElements(Mask, WidenedMask))
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if(SDValue Op = lowerV4X128VectorShuffle(DL, VT, V1, V2, WidenedMask, DAG))
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return Op;
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// X86 has dedicated unpack instructions that can handle specific blend
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// operations: UNPCKH and UNPCKL.
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if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 2, 10, 4, 12, 6, 14}))
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return DAG.getNode(X86ISD::UNPCKL, DL, VT, V1, V2);
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return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f64, V1, V2);
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if (isShuffleEquivalent(V1, V2, Mask, {1, 9, 3, 11, 5, 13, 7, 15}))
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return DAG.getNode(X86ISD::UNPCKH, DL, VT, V1, V2);
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return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f64, V1, V2);
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if (SDValue Op = lowerVectorShuffleWithVALIGN(DL, VT, Mask, V1, V2, DAG))
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return Op;
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if (SDValue Op = lowerVectorShuffleWithSHUFPD(DL, VT, Mask, V1, V2, DAG))
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return Op;
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// PERMILPD instruction - mask 0/1, 0/1, 2/3, 2/3, 4/5, 4/5, 6/7, 6/7
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if (isSingleInputShuffleMask(Mask)) {
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if (!is128BitLaneCrossingShuffleMask(VT, Mask))
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return DAG.getNode(X86ISD::VPERMILPI, DL, VT, V1,
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get1bitLaneShuffleImm8ForMask(Mask, DL, DAG));
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SmallVector<int, 4> RepeatedMask;
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if (is256BitLaneRepeatedShuffleMask(VT, Mask, RepeatedMask))
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return DAG.getNode(X86ISD::VPERMI, DL, VT, V1,
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getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
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}
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return lowerVectorShuffleWithPERMV(DL, VT, Mask, V1, V2, DAG);
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// FIXME: Implement direct support for this type!
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return splitAndLowerVectorShuffle(DL, MVT::v8f64, V1, V2, Mask, DAG);
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}
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/// \brief Handle lowering of 16-lane 32-bit integer shuffles.
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static SDValue lowerV16X32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
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/// \brief Handle lowering of 16-lane 32-bit floating point shuffles.
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static SDValue lowerV16F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
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const X86Subtarget *Subtarget,
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SelectionDAG &DAG) {
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MVT VT = Op.getSimpleValueType();
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SDLoc DL(Op);
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assert((V1.getSimpleValueType() == MVT::v16i32 ||
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V1.getSimpleValueType() == MVT::v16f32) && "Bad operand type!");
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assert((V2.getSimpleValueType() == MVT::v16i32 ||
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V2.getSimpleValueType() == MVT::v16f32) && "Bad operand type!");
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assert(V1.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
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assert(V2.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
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ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
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ArrayRef<int> Mask = SVOp->getMask();
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assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
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@ -10253,39 +10107,67 @@ static SDValue lowerV16X32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
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0, 16, 1, 17, 4, 20, 5, 21,
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// Second 128-bit lane.
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8, 24, 9, 25, 12, 28, 13, 29}))
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return DAG.getNode(X86ISD::UNPCKL, DL, VT, V1, V2);
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return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16f32, V1, V2);
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if (isShuffleEquivalent(V1, V2, Mask,
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{// First 128-bit lane.
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2, 18, 3, 19, 6, 22, 7, 23,
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// Second 128-bit lane.
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10, 26, 11, 27, 14, 30, 15, 31}))
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return DAG.getNode(X86ISD::UNPCKH, DL, VT, V1, V2);
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return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16f32, V1, V2);
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if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2, 4, 4, 6, 6, 8, 8, 10, 10,
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12, 12, 14, 14}))
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return DAG.getNode(X86ISD::MOVSLDUP, DL, VT, V1);
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if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3, 5, 5, 7, 7, 9, 9, 11, 11,
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13, 13, 15, 15}))
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return DAG.getNode(X86ISD::MOVSHDUP, DL, VT, V1);
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// FIXME: Implement direct support for this type!
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return splitAndLowerVectorShuffle(DL, MVT::v16f32, V1, V2, Mask, DAG);
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}
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SmallVector<int, 4> RepeatedMask;
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if (is128BitLaneRepeatedShuffleMask(VT, Mask, RepeatedMask)) {
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if (isSingleInputShuffleMask(Mask)) {
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unsigned Opc = VT.isInteger() ? X86ISD::PSHUFD : X86ISD::VPERMILPI;
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return DAG.getNode(Opc, DL, VT, V1,
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getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
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}
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/// \brief Handle lowering of 8-lane 64-bit integer shuffles.
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static SDValue lowerV8I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
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const X86Subtarget *Subtarget,
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SelectionDAG &DAG) {
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SDLoc DL(Op);
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assert(V1.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
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assert(V2.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
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ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
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ArrayRef<int> Mask = SVOp->getMask();
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assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
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for (int i = 0; i < 4; ++i)
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if (RepeatedMask[i] >= 16)
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RepeatedMask[i] -= 12;
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return lowerVectorShuffleWithSHUFPS(DL, VT, RepeatedMask, V1, V2, DAG);
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}
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// X86 has dedicated unpack instructions that can handle specific blend
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// operations: UNPCKH and UNPCKL.
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if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 2, 10, 4, 12, 6, 14}))
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return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i64, V1, V2);
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if (isShuffleEquivalent(V1, V2, Mask, {1, 9, 3, 11, 5, 13, 7, 15}))
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return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i64, V1, V2);
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if (SDValue Op = lowerVectorShuffleWithVALIGN(DL, VT, Mask, V1, V2, DAG))
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return Op;
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// FIXME: Implement direct support for this type!
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return splitAndLowerVectorShuffle(DL, MVT::v8i64, V1, V2, Mask, DAG);
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}
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return lowerVectorShuffleWithPERMV(DL, VT, Mask, V1, V2, DAG);
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/// \brief Handle lowering of 16-lane 32-bit integer shuffles.
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static SDValue lowerV16I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
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const X86Subtarget *Subtarget,
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SelectionDAG &DAG) {
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SDLoc DL(Op);
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assert(V1.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
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assert(V2.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
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ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
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ArrayRef<int> Mask = SVOp->getMask();
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assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
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// Use dedicated unpack instructions for masks that match their pattern.
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if (isShuffleEquivalent(V1, V2, Mask,
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{// First 128-bit lane.
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0, 16, 1, 17, 4, 20, 5, 21,
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// Second 128-bit lane.
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8, 24, 9, 25, 12, 28, 13, 29}))
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return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i32, V1, V2);
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if (isShuffleEquivalent(V1, V2, Mask,
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{// First 128-bit lane.
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2, 18, 3, 19, 6, 22, 7, 23,
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// Second 128-bit lane.
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10, 26, 11, 27, 14, 30, 15, 31}))
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return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i32, V1, V2);
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// FIXME: Implement direct support for this type!
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return splitAndLowerVectorShuffle(DL, MVT::v16i32, V1, V2, Mask, DAG);
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}
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/// \brief Handle lowering of 32-lane 16-bit integer shuffles.
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@ -10345,11 +10227,13 @@ static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
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// the requisite ISA extensions for that element type are available.
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switch (VT.SimpleTy) {
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case MVT::v8f64:
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case MVT::v8i64:
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return lowerV8X64VectorShuffle(Op, V1, V2, Subtarget, DAG);
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return lowerV8F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
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case MVT::v16f32:
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return lowerV16F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
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case MVT::v8i64:
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return lowerV8I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
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case MVT::v16i32:
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return lowerV16X32VectorShuffle(Op, V1, V2, Subtarget, DAG);
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return lowerV16I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
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case MVT::v32i16:
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if (Subtarget->hasBWI())
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return lowerV32I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
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@ -1,15 +1,5 @@
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; RUN: llc < %s -march=x86-64 -mtriple=x86_64-apple-darwin -mcpu=knl | FileCheck %s
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define <16 x i32> @test1(i32* %x) {
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; CHECK-LABEL: test1:
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; CHECK: vmovd (%rdi), %xmm
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; CHECK: vmovdqa32
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; CHECK: vpermt2d %zmm
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%y = load i32, i32* %x, align 4
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%res = insertelement <16 x i32>zeroinitializer, i32 %y, i32 4
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ret <16 x i32>%res
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}
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define <16 x i32> @test2(<16 x i32> %x) {
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; CHECK-LABEL: test2:
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; CHECK: ## BB#0:
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@ -1,392 +0,0 @@
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl | FileCheck %s
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=skx | FileCheck %s --check-prefix=CHECK-SKX
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; CHECK-LABEL: test1:
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; CHECK: vpermps
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; CHECK: ret
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define <16 x float> @test1(<16 x float> %a) nounwind {
|
||||
%c = shufflevector <16 x float> %a, <16 x float> undef, <16 x i32> <i32 2, i32 5, i32 undef, i32 undef, i32 7, i32 undef, i32 10, i32 1, i32 0, i32 5, i32 undef, i32 4, i32 7, i32 undef, i32 10, i32 1>
|
||||
ret <16 x float> %c
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test2:
|
||||
; CHECK: vpermd
|
||||
; CHECK: ret
|
||||
define <16 x i32> @test2(<16 x i32> %a) nounwind {
|
||||
%c = shufflevector <16 x i32> %a, <16 x i32> undef, <16 x i32> <i32 2, i32 5, i32 undef, i32 undef, i32 7, i32 undef, i32 10, i32 1, i32 0, i32 5, i32 undef, i32 4, i32 7, i32 undef, i32 10, i32 1>
|
||||
ret <16 x i32> %c
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test3:
|
||||
; CHECK: vpermq
|
||||
; CHECK: ret
|
||||
define <8 x i64> @test3(<8 x i64> %a) nounwind {
|
||||
%c = shufflevector <8 x i64> %a, <8 x i64> undef, <8 x i32> <i32 2, i32 5, i32 1, i32 undef, i32 7, i32 undef, i32 3, i32 1>
|
||||
ret <8 x i64> %c
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test4:
|
||||
; CHECK: vpermpd
|
||||
; CHECK: ret
|
||||
define <8 x double> @test4(<8 x double> %a) nounwind {
|
||||
%c = shufflevector <8 x double> %a, <8 x double> undef, <8 x i32> <i32 1, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
|
||||
ret <8 x double> %c
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test5:
|
||||
; CHECK: vpermt2pd
|
||||
; CHECK: ret
|
||||
define <8 x double> @test5(<8 x double> %a, <8 x double> %b) nounwind {
|
||||
%c = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 2, i32 8, i32 0, i32 1, i32 6, i32 10, i32 4, i32 5>
|
||||
ret <8 x double> %c
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test6:
|
||||
; CHECK: vpermq $30
|
||||
; CHECK: ret
|
||||
define <8 x i64> @test6(<8 x i64> %a) nounwind {
|
||||
%c = shufflevector <8 x i64> %a, <8 x i64> undef, <8 x i32> <i32 2, i32 3, i32 1, i32 0, i32 6, i32 7, i32 5, i32 4>
|
||||
ret <8 x i64> %c
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test7:
|
||||
; CHECK: vpermt2q
|
||||
; CHECK: ret
|
||||
define <8 x i64> @test7(<8 x i64> %a, <8 x i64> %b) nounwind {
|
||||
%c = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 2, i32 8, i32 0, i32 1, i32 6, i32 10, i32 4, i32 5>
|
||||
ret <8 x i64> %c
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test8:
|
||||
; CHECK: vpermt2d
|
||||
; CHECK: ret
|
||||
define <16 x i32> @test8(<16 x i32> %a, <16 x i32> %b) nounwind {
|
||||
%c = shufflevector <16 x i32> %a, <16 x i32> %b, <16 x i32> <i32 15, i32 31, i32 14, i32 22, i32 13, i32 29, i32 4, i32 28, i32 11, i32 27, i32 10, i32 26, i32 9, i32 25, i32 8, i32 24>
|
||||
ret <16 x i32> %c
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test9:
|
||||
; CHECK: vpermt2ps
|
||||
; CHECK: ret
|
||||
define <16 x float> @test9(<16 x float> %a, <16 x float> %b) nounwind {
|
||||
%c = shufflevector <16 x float> %a, <16 x float> %b, <16 x i32> <i32 15, i32 31, i32 14, i32 22, i32 13, i32 29, i32 4, i32 28, i32 11, i32 27, i32 10, i32 26, i32 9, i32 25, i32 8, i32 24>
|
||||
ret <16 x float> %c
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test10:
|
||||
; CHECK: vpermt2ps (
|
||||
; CHECK: ret
|
||||
define <16 x float> @test10(<16 x float> %a, <16 x float>* %b) nounwind {
|
||||
%c = load <16 x float>, <16 x float>* %b
|
||||
%d = shufflevector <16 x float> %a, <16 x float> %c, <16 x i32> <i32 15, i32 31, i32 14, i32 22, i32 13, i32 29, i32 4, i32 28, i32 11, i32 27, i32 10, i32 26, i32 9, i32 25, i32 8, i32 24>
|
||||
ret <16 x float> %d
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test11:
|
||||
; CHECK: vpermt2d
|
||||
; CHECK: ret
|
||||
define <16 x i32> @test11(<16 x i32> %a, <16 x i32>* %b) nounwind {
|
||||
%c = load <16 x i32>, <16 x i32>* %b
|
||||
%d = shufflevector <16 x i32> %a, <16 x i32> %c, <16 x i32> <i32 15, i32 31, i32 14, i32 22, i32 13, i32 29, i32 4, i32 28, i32 11, i32 27, i32 10, i32 26, i32 9, i32 25, i32 8, i32 24>
|
||||
ret <16 x i32> %d
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test13
|
||||
; CHECK: vpermilps $177, %zmm
|
||||
; CHECK: ret
|
||||
define <16 x float> @test13(<16 x float> %a) {
|
||||
%b = shufflevector <16 x float> %a, <16 x float> undef, <16 x i32><i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14>
|
||||
ret <16 x float> %b
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test14
|
||||
; CHECK: vpermilpd $203, %zmm
|
||||
; CHECK: ret
|
||||
define <8 x double> @test14(<8 x double> %a) {
|
||||
%b = shufflevector <8 x double> %a, <8 x double> undef, <8 x i32><i32 1, i32 1, i32 2, i32 3, i32 4, i32 4, i32 7, i32 7>
|
||||
ret <8 x double> %b
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test15
|
||||
; CHECK: vpshufd $177, %zmm
|
||||
; CHECK: ret
|
||||
define <16 x i32> @test15(<16 x i32> %a) {
|
||||
; mask 1-0-3-2 = 10110001 = 0xb1 = 177
|
||||
%b = shufflevector <16 x i32> %a, <16 x i32> undef, <16 x i32><i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14>
|
||||
ret <16 x i32> %b
|
||||
}
|
||||
; CHECK-LABEL: test16
|
||||
; CHECK: valignq $3, %zmm0, %zmm1
|
||||
; CHECK: ret
|
||||
define <8 x double> @test16(<8 x double> %a, <8 x double> %b) nounwind {
|
||||
%c = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10>
|
||||
ret <8 x double> %c
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test17
|
||||
; CHECK: vshufpd $19, %zmm1, %zmm0
|
||||
; CHECK: ret
|
||||
define <8 x double> @test17(<8 x double> %a, <8 x double> %b) nounwind {
|
||||
%c = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 1, i32 9, i32 2, i32 10, i32 5, i32 undef, i32 undef, i32 undef>
|
||||
ret <8 x double> %c
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test18
|
||||
; CHECK: vpunpckhdq %zmm
|
||||
; CHECK: ret
|
||||
define <16 x i32> @test18(<16 x i32> %a, <16 x i32> %c) {
|
||||
%b = shufflevector <16 x i32> %a, <16 x i32> %c, <16 x i32><i32 2, i32 18, i32 3, i32 19, i32 6, i32 22, i32 7, i32 23, i32 10, i32 26, i32 11, i32 27, i32 14, i32 30, i32 15, i32 31>
|
||||
ret <16 x i32> %b
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test19
|
||||
; CHECK: vpunpckldq %zmm
|
||||
; CHECK: ret
|
||||
define <16 x i32> @test19(<16 x i32> %a, <16 x i32> %c) {
|
||||
%b = shufflevector <16 x i32> %a, <16 x i32> %c, <16 x i32><i32 0, i32 16, i32 1, i32 17, i32 4, i32 20, i32 5, i32 21, i32 8, i32 24, i32 9, i32 25, i32 12, i32 28, i32 13, i32 29>
|
||||
ret <16 x i32> %b
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test20
|
||||
; CHECK: vpunpckhqdq %zmm
|
||||
; CHECK: ret
|
||||
define <8 x i64> @test20(<8 x i64> %a, <8 x i64> %c) {
|
||||
%b = shufflevector <8 x i64> %a, <8 x i64> %c, <8 x i32><i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15>
|
||||
ret <8 x i64> %b
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test21
|
||||
; CHECK: vbroadcastsd %xmm0, %zmm
|
||||
; CHECK: ret
|
||||
define <8 x double> @test21(<8 x double> %a, <8 x double> %b) {
|
||||
%shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
|
||||
ret <8 x double> %shuffle
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test22
|
||||
; CHECK: vpbroadcastq %xmm0, %zmm
|
||||
; CHECK: ret
|
||||
define <8 x i64> @test22(<8 x i64> %a, <8 x i64> %b) {
|
||||
%shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
|
||||
ret <8 x i64> %shuffle
|
||||
}
|
||||
|
||||
; CHECK-LABEL: @test23
|
||||
; CHECK: vshufps
|
||||
; CHECK: vshufps
|
||||
; CHECK: ret
|
||||
define <16 x i32> @test23(<16 x i32> %a, <16 x i32> %b) nounwind {
|
||||
%c = shufflevector <16 x i32> %a, <16 x i32> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 19, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
|
||||
ret <16 x i32> %c
|
||||
}
|
||||
|
||||
; CHECK-LABEL: @test24
|
||||
; CHECK: vpermt2d
|
||||
; CHECK: ret
|
||||
define <16 x i32> @test24(<16 x i32> %a, <16 x i32> %b) nounwind {
|
||||
%c = shufflevector <16 x i32> %a, <16 x i32> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 19, i32 25, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
|
||||
ret <16 x i32> %c
|
||||
}
|
||||
|
||||
; CHECK-LABEL: @test25
|
||||
; CHECK: vshufps $52
|
||||
; CHECK: ret
|
||||
define <16 x i32> @test25(<16 x i32> %a, <16 x i32> %b) nounwind {
|
||||
; mask - 0-1-3-0 00110100 = 0x34 = 52
|
||||
%c = shufflevector <16 x i32> %a, <16 x i32> %b, <16 x i32> <i32 0, i32 1, i32 19, i32 16, i32 4, i32 5, i32 23, i32 undef, i32 8, i32 9, i32 27, i32 undef, i32 12, i32 13, i32 undef, i32 undef>
|
||||
ret <16 x i32> %c
|
||||
}
|
||||
|
||||
; CHECK-LABEL: @test26
|
||||
; CHECK: vmovshdup
|
||||
; CHECK: ret
|
||||
define <16 x i32> @test26(<16 x i32> %a) nounwind {
|
||||
%c = shufflevector <16 x i32> %a, <16 x i32> undef, <16 x i32> <i32 1, i32 1, i32 3, i32 3, i32 5, i32 5, i32 7, i32 undef, i32 9, i32 9, i32 undef, i32 11, i32 13, i32 undef, i32 undef, i32 undef>
|
||||
ret <16 x i32> %c
|
||||
}
|
||||
|
||||
; CHECK-LABEL: @test27
|
||||
; CHECK: ret
|
||||
define <16 x i32> @test27(<4 x i32>%a) {
|
||||
%res = shufflevector <4 x i32> %a, <4 x i32> undef, <16 x i32> <i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
|
||||
ret <16 x i32> %res
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test28
|
||||
; CHECK: vpshufhw $177, %ymm
|
||||
; CHECK: ret
|
||||
define <16 x i16> @test28(<16 x i16> %a) {
|
||||
%b = shufflevector <16 x i16> %a, <16 x i16> undef, <16 x i32><i32 0, i32 1, i32 2, i32 3, i32 5, i32 4, i32 7, i32 6, i32 8, i32 9, i32 10, i32 11, i32 13, i32 12, i32 15, i32 14>
|
||||
ret <16 x i16> %b
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test29
|
||||
; CHECK: vunpcklps %zmm
|
||||
; CHECK: ret
|
||||
define <16 x float> @test29(<16 x float> %a, <16 x float> %c) {
|
||||
%b = shufflevector <16 x float> %a, <16 x float> %c, <16 x i32><i32 0, i32 16, i32 1, i32 17, i32 4, i32 20, i32 5, i32 21, i32 8, i32 24, i32 9, i32 25, i32 12, i32 28, i32 13, i32 29>
|
||||
ret <16 x float> %b
|
||||
}
|
||||
|
||||
; CHECK-LABEL: @test30
|
||||
; CHECK: vshufps $144, %zmm
|
||||
; CHECK: ret
|
||||
define <16 x float> @test30(<16 x float> %a, <16 x float> %c) {
|
||||
%b = shufflevector <16 x float> %a, <16 x float> %c, <16 x i32><i32 0, i32 0, i32 17, i32 18, i32 4, i32 4, i32 21, i32 22, i32 8, i32 8, i32 25, i32 26, i32 12, i32 12, i32 29, i32 30>
|
||||
ret <16 x float> %b
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test31
|
||||
; CHECK: valignd $3, %zmm0, %zmm1
|
||||
; CHECK: ret
|
||||
define <16 x i32> @test31(<16 x i32> %a, <16 x i32> %b) nounwind {
|
||||
%c = shufflevector <16 x i32> %a, <16 x i32> %b, <16 x i32> <i32 3, i32 4, i32 5, i32 undef, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18>
|
||||
ret <16 x i32> %c
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test32
|
||||
; CHECK: vshufpd $99, %zmm0, %zmm1
|
||||
; CHECK: ret
|
||||
define <8 x double> @test32(<8 x double> %a, <8 x double> %b) nounwind {
|
||||
%c = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 9, i32 1, i32 10, i32 2, i32 undef, i32 5, i32 15, i32 undef>
|
||||
ret <8 x double> %c
|
||||
}
|
||||
|
||||
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl | FileCheck %s
|
||||
define <8 x double> @test_vshuff64x2_512(<8 x double> %x, <8 x double> %x1) nounwind {
|
||||
; CHECK-LABEL: test_vshuff64x2_512:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: vshuff64x2 $136, %zmm0, %zmm0, %zmm0
|
||||
; CHECK-NEXT: retq
|
||||
%res = shufflevector <8 x double> %x, <8 x double> %x1, <8 x i32> <i32 0, i32 1, i32 4, i32 5, i32 0, i32 1, i32 4, i32 5>
|
||||
ret <8 x double> %res
|
||||
}
|
||||
|
||||
define <8 x double> @test_vshuff64x2_512_mask(<8 x double> %x, <8 x double> %x1, <8 x i1> %mask) nounwind {
|
||||
; CHECK-LABEL: test_vshuff64x2_512_mask:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: vpmovsxwq %xmm2, %zmm1
|
||||
; CHECK-NEXT: vpandq {{.*}}(%rip){1to8}, %zmm1, %zmm1
|
||||
; CHECK-NEXT: vptestmq %zmm1, %zmm1, %k1
|
||||
; CHECK-NEXT: vshuff64x2 $136, %zmm0, %zmm0, %zmm0 {%k1} {z}
|
||||
; CHECK-NEXT: retq
|
||||
%y = shufflevector <8 x double> %x, <8 x double> %x1, <8 x i32> <i32 0, i32 1, i32 4, i32 5, i32 0, i32 1, i32 4, i32 5>
|
||||
%res = select <8 x i1> %mask, <8 x double> %y, <8 x double> zeroinitializer
|
||||
ret <8 x double> %res
|
||||
}
|
||||
|
||||
define <8 x i64> @test_vshufi64x2_512_mask(<8 x i64> %x, <8 x i64> %x1, <8 x i1> %mask) nounwind {
|
||||
; CHECK-LABEL: test_vshufi64x2_512_mask:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: vpmovsxwq %xmm2, %zmm1
|
||||
; CHECK-NEXT: vpandq {{.*}}(%rip){1to8}, %zmm1, %zmm1
|
||||
; CHECK-NEXT: vptestmq %zmm1, %zmm1, %k1
|
||||
; CHECK-NEXT: vshufi64x2 $168, %zmm0, %zmm0, %zmm0 {%k1}
|
||||
; CHECK-NEXT: retq
|
||||
%y = shufflevector <8 x i64> %x, <8 x i64> %x1, <8 x i32> <i32 0, i32 1, i32 4, i32 5, i32 4, i32 5, i32 4, i32 5>
|
||||
%res = select <8 x i1> %mask, <8 x i64> %y, <8 x i64> %x
|
||||
ret <8 x i64> %res
|
||||
}
|
||||
|
||||
define <8 x double> @test_vshuff64x2_512_mem(<8 x double> %x, <8 x double> *%ptr) nounwind {
|
||||
; CHECK-LABEL: test_vshuff64x2_512_mem:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: vshuff64x2 $40, %zmm0, %zmm0, %zmm0
|
||||
; CHECK-NEXT: retq
|
||||
%x1 = load <8 x double>,<8 x double> *%ptr,align 1
|
||||
%res = shufflevector <8 x double> %x, <8 x double> %x1, <8 x i32> <i32 0, i32 1, i32 4, i32 5, i32 4, i32 5, i32 0, i32 1>
|
||||
ret <8 x double> %res
|
||||
}
|
||||
|
||||
define <16 x float> @test_vshuff32x4_512_mem(<16 x float> %x, <16 x float> *%ptr) nounwind {
|
||||
; CHECK-LABEL: test_vshuff32x4_512_mem:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: vshuff64x2 $20, %zmm0, %zmm0, %zmm0
|
||||
; CHECK-NEXT: retq
|
||||
%x1 = load <16 x float>,<16 x float> *%ptr,align 1
|
||||
%res = shufflevector <16 x float> %x, <16 x float> %x1, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
|
||||
ret <16 x float> %res
|
||||
}
|
||||
|
||||
define <16 x i32> @test_align_v16i32_rr(<16 x i32> %a, <16 x i32> %b) nounwind {
|
||||
; CHECK-LABEL: test_align_v16i32_rr:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: valignd $3, %zmm0, %zmm1, %zmm0
|
||||
; CHECK-NEXT: retq
|
||||
%c = shufflevector <16 x i32> %a, <16 x i32> %b, <16 x i32> <i32 3, i32 4, i32 5, i32 undef, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18>
|
||||
ret <16 x i32> %c
|
||||
}
|
||||
|
||||
define <16 x i32> @test_align_v16i32_rm(<16 x i32>* %a.ptr, <16 x i32> %b) nounwind {
|
||||
; CHECK-LABEL: test_align_v16i32_rm:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: valignd $3, (%rdi), %zmm0, %zmm0
|
||||
; CHECK-NEXT: retq
|
||||
%a = load <16 x i32>, <16 x i32>* %a.ptr
|
||||
%c = shufflevector <16 x i32> %a, <16 x i32> %b, <16 x i32> <i32 3, i32 4, i32 5, i32 undef, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18>
|
||||
ret <16 x i32> %c
|
||||
}
|
||||
|
||||
define <16 x i32> @test_align_v16i32_rm_mask(<16 x i32>* %a.ptr, <16 x i32> %b, <16 x i1> %mask) nounwind {
|
||||
; CHECK-LABEL: test_align_v16i32_rm_mask:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: vpmovsxbd %xmm1, %zmm1
|
||||
; CHECK-NEXT: vpandd {{.*}}(%rip){1to16}, %zmm1, %zmm1
|
||||
; CHECK-NEXT: vptestmd %zmm1, %zmm1, %k1
|
||||
; CHECK-NEXT: vmovdqa32 (%rdi), %zmm1
|
||||
; CHECK-NEXT: valignd $3, %zmm1, %zmm0, %zmm1 {%k1}
|
||||
; CHECK-NEXT: vmovaps %zmm1, %zmm0
|
||||
; CHECK-NEXT: retq
|
||||
;
|
||||
; CHECK-SKX-LABEL: test_align_v16i32_rm_mask:
|
||||
; CHECK-SKX: ## BB#0:
|
||||
; CHECK-SKX-NEXT: vpmovb2m %xmm1, %k1
|
||||
; CHECK-SKX-NEXT: vmovdqa32 (%rdi), %zmm1
|
||||
; CHECK-SKX-NEXT: valignd $3, %zmm1, %zmm0, %zmm1 {%k1}
|
||||
; CHECK-SKX-NEXT: vmovaps %zmm1, %zmm0
|
||||
; CHECK-SKX-NEXT: retq
|
||||
%a = load <16 x i32>, <16 x i32>* %a.ptr
|
||||
%c = shufflevector <16 x i32> %a, <16 x i32> %b, <16 x i32> <i32 3, i32 4, i32 5, i32 undef, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18>
|
||||
%res = select <16 x i1> %mask,<16 x i32> %c, <16 x i32> %a
|
||||
ret <16 x i32> %res
|
||||
}
|
||||
|
||||
define <8 x double> @test_align_v8f64_rr(<8 x double> %a, <8 x double> %b) nounwind {
|
||||
; CHECK-LABEL: test_align_v8f64_rr:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: valignq $3, %zmm0, %zmm1, %zmm0
|
||||
; CHECK-NEXT: retq
|
||||
%c = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10>
|
||||
ret <8 x double> %c
|
||||
}
|
||||
|
||||
define <8 x double> @test_align_v18f64_rm(<8 x double>* %a.ptr, <8 x double> %b) nounwind {
|
||||
; CHECK-LABEL: test_align_v18f64_rm:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: valignq $3, (%rdi), %zmm0, %zmm0
|
||||
; CHECK-NEXT: retq
|
||||
%a = load <8 x double>, <8 x double>* %a.ptr
|
||||
%c = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10>
|
||||
ret <8 x double> %c
|
||||
}
|
||||
|
||||
define <8 x double> @test_align_v18f64_rm_mask(<8 x double>* %a.ptr, <8 x double> %b, <8 x i1> %mask) nounwind {
|
||||
; CHECK-LABEL: test_align_v18f64_rm_mask:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: vpmovsxwq %xmm1, %zmm1
|
||||
; CHECK-NEXT: vpandq {{.*}}(%rip){1to8}, %zmm1, %zmm1
|
||||
; CHECK-NEXT: vptestmq %zmm1, %zmm1, %k1
|
||||
; CHECK-NEXT: valignq $3, (%rdi), %zmm0, %zmm0 {%k1} {z}
|
||||
; CHECK-NEXT: retq
|
||||
;
|
||||
; CHECK-SKX-LABEL: test_align_v18f64_rm_mask:
|
||||
; CHECK-SKX: ## BB#0:
|
||||
; CHECK-SKX-NEXT: vpmovw2m %xmm1, %k1
|
||||
; CHECK-SKX-NEXT: valignq $3, (%rdi), %zmm0, %zmm0 {%k1} {z}
|
||||
; CHECK-SKX-NEXT: retq
|
||||
%a = load <8 x double>, <8 x double>* %a.ptr
|
||||
%c = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10>
|
||||
%res = select <8 x i1> %mask,<8 x double> %c, <8 x double> zeroinitializer
|
||||
ret <8 x double> %res
|
||||
}
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue
Block a user