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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-22 10:29:35 +00:00
Remove the TargetRegisterClass member from CalleeSavedInfo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105344 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
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962f549d20
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@ -33,16 +33,14 @@ class BitVector;
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/// callee saved register in the current frame.
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class CalleeSavedInfo {
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unsigned Reg;
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const TargetRegisterClass *RegClass;
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int FrameIdx;
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public:
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CalleeSavedInfo(unsigned R, const TargetRegisterClass *RC, int FI = 0)
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: Reg(R), RegClass(RC), FrameIdx(FI) {}
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CalleeSavedInfo(unsigned R, int FI = 0)
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: Reg(R), FrameIdx(FI) {}
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// Accessors.
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unsigned getReg() const { return Reg; }
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const TargetRegisterClass *getRegClass() const { return RegClass; }
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int getFrameIdx() const { return FrameIdx; }
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void setFrameIdx(int FI) { FrameIdx = FI; }
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};
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@ -205,15 +205,14 @@ void PEI::calculateCalleeSavedRegisters(MachineFunction &Fn) {
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std::vector<CalleeSavedInfo> CSI;
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for (unsigned i = 0; CSRegs[i]; ++i) {
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unsigned Reg = CSRegs[i];
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const TargetRegisterClass *RC = RegInfo->getMinimalPhysRegClass(Reg);
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if (Fn.getRegInfo().isPhysRegUsed(Reg)) {
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// If the reg is modified, save it!
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CSI.push_back(CalleeSavedInfo(Reg, RC));
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CSI.push_back(CalleeSavedInfo(Reg));
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} else {
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for (const unsigned *AliasSet = RegInfo->getAliasSet(Reg);
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*AliasSet; ++AliasSet) { // Check alias registers too.
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if (Fn.getRegInfo().isPhysRegUsed(*AliasSet)) {
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CSI.push_back(CalleeSavedInfo(Reg, RC));
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CSI.push_back(CalleeSavedInfo(Reg));
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break;
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}
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}
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@ -232,7 +231,7 @@ void PEI::calculateCalleeSavedRegisters(MachineFunction &Fn) {
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for (std::vector<CalleeSavedInfo>::iterator
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I = CSI.begin(), E = CSI.end(); I != E; ++I) {
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unsigned Reg = I->getReg();
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const TargetRegisterClass *RC = I->getRegClass();
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const TargetRegisterClass *RC = RegInfo->getMinimalPhysRegClass(Reg);
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int FrameIdx;
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if (RegInfo->hasReservedSpillSlot(Fn, Reg, FrameIdx)) {
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@ -299,8 +298,10 @@ void PEI::insertCSRSpillsAndRestores(MachineFunction &Fn) {
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EntryBlock->addLiveIn(CSI[i].getReg());
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// Insert the spill to the stack frame.
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TII.storeRegToStackSlot(*EntryBlock, I, CSI[i].getReg(), true,
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CSI[i].getFrameIdx(), CSI[i].getRegClass(),TRI);
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unsigned Reg = CSI[i].getReg();
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const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
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TII.storeRegToStackSlot(*EntryBlock, I, Reg, true,
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CSI[i].getFrameIdx(), RC, TRI);
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}
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}
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@ -324,9 +325,11 @@ void PEI::insertCSRSpillsAndRestores(MachineFunction &Fn) {
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// terminators that preceed it.
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if (!TII.restoreCalleeSavedRegisters(*MBB, I, CSI, TRI)) {
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for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
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TII.loadRegFromStackSlot(*MBB, I, CSI[i].getReg(),
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unsigned Reg = CSI[i].getReg();
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const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
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TII.loadRegFromStackSlot(*MBB, I, Reg,
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CSI[i].getFrameIdx(),
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CSI[i].getRegClass(), TRI);
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RC, TRI);
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assert(I != MBB->begin() &&
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"loadRegFromStackSlot didn't insert any code!");
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// Insert in reverse order. loadRegFromStackSlot can insert
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@ -370,10 +373,12 @@ void PEI::insertCSRSpillsAndRestores(MachineFunction &Fn) {
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MBB->addLiveIn(blockCSI[i].getReg());
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// Insert the spill to the stack frame.
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TII.storeRegToStackSlot(*MBB, I, blockCSI[i].getReg(),
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unsigned Reg = blockCSI[i].getReg();
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const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
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TII.storeRegToStackSlot(*MBB, I, Reg,
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true,
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blockCSI[i].getFrameIdx(),
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blockCSI[i].getRegClass(), TRI);
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RC, TRI);
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}
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}
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@ -419,9 +424,11 @@ void PEI::insertCSRSpillsAndRestores(MachineFunction &Fn) {
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// Restore all registers immediately before the return and any
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// terminators that preceed it.
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for (unsigned i = 0, e = blockCSI.size(); i != e; ++i) {
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TII.loadRegFromStackSlot(*MBB, I, blockCSI[i].getReg(),
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unsigned Reg = blockCSI[i].getReg();
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const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
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TII.loadRegFromStackSlot(*MBB, I, Reg,
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blockCSI[i].getFrameIdx(),
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blockCSI[i].getRegClass(), TRI);
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RC, TRI);
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assert(I != MBB->begin() &&
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"loadRegFromStackSlot didn't insert any code!");
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// Insert in reverse order. loadRegFromStackSlot can insert
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@ -227,8 +227,9 @@ ARMBaseInstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
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// Insert the spill to the stack frame. The register is killed at the spill
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//
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const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
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storeRegToStackSlot(MBB, MI, Reg, isKill,
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CSI[i].getFrameIdx(), CSI[i].getRegClass(), TRI);
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CSI[i].getFrameIdx(), RC, TRI);
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}
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return true;
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}
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@ -145,8 +145,9 @@ void MBlazeAsmPrinter::printSavedRegsBitmask(raw_ostream &O) {
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const MachineFrameInfo *MFI = MF->getFrameInfo();
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const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
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for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
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unsigned RegNum = MBlazeRegisterInfo::getRegisterNumbering(CSI[i].getReg());
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if (CSI[i].getRegClass() == MBlaze::CPURegsRegisterClass)
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unsigned Reg = CSI[i].getReg();
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unsigned RegNum = MBlazeRegisterInfo::getRegisterNumbering(Reg);
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if (MBlaze::CPURegsRegisterClass->contains(Reg))
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CPUBitmask |= (1 << RegNum);
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}
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@ -133,8 +133,9 @@ void MipsAsmPrinter::printSavedRegsBitmask(raw_ostream &O) {
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const MachineFrameInfo *MFI = MF->getFrameInfo();
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const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
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for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
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unsigned RegNum = MipsRegisterInfo::getRegisterNumbering(CSI[i].getReg());
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if (CSI[i].getRegClass() == Mips::CPURegsRegisterClass)
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unsigned Reg = CSI[i].getReg();
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unsigned RegNum = MipsRegisterInfo::getRegisterNumbering(Reg);
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if (Mips::CPURegsRegisterClass->contains(Reg))
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CPUBitmask |= (1 << RegNum);
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else
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FPUBitmask |= (1 << RegNum);
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@ -251,7 +251,8 @@ void MipsRegisterInfo::adjustMipsStackFrame(MachineFunction &MF) const
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StackOffset = ((StackOffset+StackAlign-1)/StackAlign*StackAlign);
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for (unsigned i = 0, e = CSI.size(); i != e ; ++i) {
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if (CSI[i].getRegClass() != Mips::CPURegsRegisterClass)
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unsigned Reg = CSI[i].getReg();
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if (!Mips::CPURegsRegisterClass->contains(Reg))
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break;
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MFI->setObjectOffset(CSI[i].getFrameIdx(), StackOffset);
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TopCPUSavedRegOff = StackOffset;
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@ -283,7 +284,8 @@ void MipsRegisterInfo::adjustMipsStackFrame(MachineFunction &MF) const
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// Adjust FPU Callee Saved Registers Area. This Area must be
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// aligned to the default Stack Alignment requirements.
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for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
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if (CSI[i].getRegClass() == Mips::CPURegsRegisterClass)
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unsigned Reg = CSI[i].getReg();
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if (Mips::CPURegsRegisterClass->contains(Reg))
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continue;
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MFI->setObjectOffset(CSI[i].getFrameIdx(), StackOffset);
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TopFPUSavedRegOff = StackOffset;
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@ -500,4 +502,3 @@ getDwarfRegNum(unsigned RegNum, bool isEH) const {
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}
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#include "MipsGenRegisterInfo.inc"
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@ -993,9 +993,7 @@ PPCRegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF)
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for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
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unsigned Reg = CSI[i].getReg();
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const TargetRegisterClass *RC = CSI[i].getRegClass();
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if (RC == PPC::GPRCRegisterClass) {
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if (PPC::GPRCRegisterClass->contains(Reg)) {
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HasGPSaveArea = true;
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GPRegs.push_back(CSI[i]);
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@ -1003,7 +1001,7 @@ PPCRegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF)
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if (Reg < MinGPR) {
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MinGPR = Reg;
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}
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} else if (RC == PPC::G8RCRegisterClass) {
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} else if (PPC::G8RCRegisterClass->contains(Reg)) {
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HasG8SaveArea = true;
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G8Regs.push_back(CSI[i]);
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@ -1011,7 +1009,7 @@ PPCRegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF)
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if (Reg < MinG8R) {
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MinG8R = Reg;
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}
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} else if (RC == PPC::F8RCRegisterClass) {
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} else if (PPC::F8RCRegisterClass->contains(Reg)) {
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HasFPSaveArea = true;
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FPRegs.push_back(CSI[i]);
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@ -1020,12 +1018,12 @@ PPCRegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF)
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MinFPR = Reg;
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}
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// FIXME SVR4: Disable CR save area for now.
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} else if ( RC == PPC::CRBITRCRegisterClass
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|| RC == PPC::CRRCRegisterClass) {
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} else if (PPC::CRBITRCRegisterClass->contains(Reg)
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|| PPC::CRRCRegisterClass->contains(Reg)) {
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// HasCRSaveArea = true;
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} else if (RC == PPC::VRSAVERCRegisterClass) {
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} else if (PPC::VRSAVERCRegisterClass->contains(Reg)) {
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HasVRSAVESaveArea = true;
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} else if (RC == PPC::VRRCRegisterClass) {
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} else if (PPC::VRRCRegisterClass->contains(Reg)) {
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HasVRSaveArea = true;
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VRegs.push_back(CSI[i]);
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@ -1106,9 +1104,10 @@ PPCRegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF)
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// which have the CR/CRBIT register class?
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// Adjust the frame index of the CR spill slot.
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for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
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const TargetRegisterClass *RC = CSI[i].getRegClass();
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unsigned Reg = CSI[i].getReg();
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if (RC == PPC::CRBITRCRegisterClass || RC == PPC::CRRCRegisterClass) {
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if (PPC::CRBITRCRegisterClass->contains(Reg) ||
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PPC::CRRCRegisterClass->contains(Reg)) {
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int FI = CSI[i].getFrameIdx();
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FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
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@ -1123,9 +1122,9 @@ PPCRegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF)
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// which have the VRSAVE register class?
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// Adjust the frame index of the VRSAVE spill slot.
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for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
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const TargetRegisterClass *RC = CSI[i].getRegClass();
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unsigned Reg = CSI[i].getReg();
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if (RC == PPC::VRSAVERCRegisterClass) {
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if (PPC::VRSAVERCRegisterClass->contains(Reg)) {
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int FI = CSI[i].getFrameIdx();
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FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
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@ -1628,4 +1627,3 @@ int PPCRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
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}
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#include "PPCGenRegisterInfo.inc"
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@ -286,8 +286,7 @@ SystemZInstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
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unsigned LowReg = 0, HighReg = 0, StartOffset = -1U, EndOffset = 0;
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for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
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unsigned Reg = CSI[i].getReg();
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const TargetRegisterClass *RegClass = CSI[i].getRegClass();
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if (RegClass != &SystemZ::FP64RegClass) {
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if (!SystemZ::FP64RegClass.contains(Reg)) {
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unsigned Offset = RegSpillOffsets[Reg];
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CalleeFrameSize += 8;
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if (StartOffset > Offset) {
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@ -332,11 +331,10 @@ SystemZInstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
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// Save FPRs
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for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
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unsigned Reg = CSI[i].getReg();
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const TargetRegisterClass *RegClass = CSI[i].getRegClass();
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if (RegClass == &SystemZ::FP64RegClass) {
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if (SystemZ::FP64RegClass.contains(Reg)) {
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MBB.addLiveIn(Reg);
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storeRegToStackSlot(MBB, MI, Reg, true, CSI[i].getFrameIdx(), RegClass,
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&RI);
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storeRegToStackSlot(MBB, MI, Reg, true, CSI[i].getFrameIdx(),
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&SystemZ::FP64RegClass, &RI);
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}
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}
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@ -361,9 +359,9 @@ SystemZInstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
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// Restore FP registers
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for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
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unsigned Reg = CSI[i].getReg();
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const TargetRegisterClass *RegClass = CSI[i].getRegClass();
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if (RegClass == &SystemZ::FP64RegClass)
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loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(), RegClass, &RI);
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if (SystemZ::FP64RegClass.contains(Reg))
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loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(),
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&SystemZ::FP64RegClass, &RI);
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}
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// Restore GP registers
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@ -2277,18 +2277,17 @@ bool X86InstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
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unsigned Opc = is64Bit ? X86::PUSH64r : X86::PUSH32r;
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for (unsigned i = CSI.size(); i != 0; --i) {
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unsigned Reg = CSI[i-1].getReg();
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const TargetRegisterClass *RegClass = CSI[i-1].getRegClass();
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// Add the callee-saved register as live-in. It's killed at the spill.
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MBB.addLiveIn(Reg);
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if (Reg == FPReg)
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// X86RegisterInfo::emitPrologue will handle spilling of frame register.
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continue;
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if (RegClass != &X86::VR128RegClass && !isWin64) {
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if (!X86::VR128RegClass.contains(Reg) && !isWin64) {
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CalleeFrameSize += SlotSize;
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BuildMI(MBB, MI, DL, get(Opc)).addReg(Reg, RegState::Kill);
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} else {
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storeRegToStackSlot(MBB, MI, Reg, true, CSI[i-1].getFrameIdx(), RegClass,
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&RI);
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storeRegToStackSlot(MBB, MI, Reg, true, CSI[i-1].getFrameIdx(),
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&X86::VR128RegClass, &RI);
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}
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}
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@ -2315,11 +2314,11 @@ bool X86InstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
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if (Reg == FPReg)
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// X86RegisterInfo::emitEpilogue will handle restoring of frame register.
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continue;
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const TargetRegisterClass *RegClass = CSI[i].getRegClass();
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if (RegClass != &X86::VR128RegClass && !isWin64) {
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if (!X86::VR128RegClass.contains(Reg) && !isWin64) {
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BuildMI(MBB, MI, DL, get(Opc), Reg);
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} else {
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loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(), RegClass, &RI);
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loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(),
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&X86::VR128RegClass, &RI);
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}
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}
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return true;
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@ -3783,4 +3782,3 @@ void X86InstrInfo::SetSSEDomain(MachineInstr *MI, unsigned Domain) const {
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void X86InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
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NopInst.setOpcode(X86::NOOP);
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}
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@ -438,8 +438,10 @@ bool XCoreInstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
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// Add the callee-saved register as live-in. It's killed at the spill.
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MBB.addLiveIn(it->getReg());
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storeRegToStackSlot(MBB, MI, it->getReg(), true,
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it->getFrameIdx(), it->getRegClass(), &RI);
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unsigned Reg = it->getReg();
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const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
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storeRegToStackSlot(MBB, MI, Reg, true,
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it->getFrameIdx(), RC, &RI);
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if (emitFrameMoves) {
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MCSymbol *SaveLabel = MF->getContext().CreateTempSymbol();
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BuildMI(MBB, MI, DL, get(XCore::DBG_LABEL)).addSym(SaveLabel);
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@ -460,10 +462,11 @@ bool XCoreInstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
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--BeforeI;
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for (std::vector<CalleeSavedInfo>::const_iterator it = CSI.begin();
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it != CSI.end(); ++it) {
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unsigned Reg = it->getReg();
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const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
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loadRegFromStackSlot(MBB, MI, it->getReg(),
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it->getFrameIdx(),
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it->getRegClass(), &RI);
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RC, &RI);
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assert(MI != MBB.begin() &&
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"loadRegFromStackSlot didn't insert any code!");
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// Insert in reverse order. loadRegFromStackSlot can insert multiple
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