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Remove the TargetRegisterClass member from CalleeSavedInfo

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105344 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Rafael Espindola 2010-06-02 20:02:30 +00:00
parent 962f549d20
commit 42d075c4fb
10 changed files with 65 additions and 59 deletions
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6
include/llvm/CodeGen/MachineFrameInfo.h
View File

@ -33,16 +33,14 @@ class BitVector;
/// callee saved register in the current frame.
class CalleeSavedInfo {
unsigned Reg;
const TargetRegisterClass *RegClass;
int FrameIdx;
public:
CalleeSavedInfo(unsigned R, const TargetRegisterClass *RC, int FI = 0)
: Reg(R), RegClass(RC), FrameIdx(FI) {}
CalleeSavedInfo(unsigned R, int FI = 0)
: Reg(R), FrameIdx(FI) {}
// Accessors.
unsigned getReg() const { return Reg; }
const TargetRegisterClass *getRegClass() const { return RegClass; }
int getFrameIdx() const { return FrameIdx; }
void setFrameIdx(int FI) { FrameIdx = FI; }
};

31
lib/CodeGen/PrologEpilogInserter.cpp
View File

@ -205,15 +205,14 @@ void PEI::calculateCalleeSavedRegisters(MachineFunction &Fn) {
std::vector<CalleeSavedInfo> CSI;
for (unsigned i = 0; CSRegs[i]; ++i) {
unsigned Reg = CSRegs[i];
const TargetRegisterClass *RC = RegInfo->getMinimalPhysRegClass(Reg);
if (Fn.getRegInfo().isPhysRegUsed(Reg)) {
// If the reg is modified, save it!
CSI.push_back(CalleeSavedInfo(Reg, RC));
CSI.push_back(CalleeSavedInfo(Reg));
} else {
for (const unsigned *AliasSet = RegInfo->getAliasSet(Reg);
*AliasSet; ++AliasSet) { // Check alias registers too.
if (Fn.getRegInfo().isPhysRegUsed(*AliasSet)) {
CSI.push_back(CalleeSavedInfo(Reg, RC));
CSI.push_back(CalleeSavedInfo(Reg));
break;
}
}
@ -232,7 +231,7 @@ void PEI::calculateCalleeSavedRegisters(MachineFunction &Fn) {
for (std::vector<CalleeSavedInfo>::iterator
I = CSI.begin(), E = CSI.end(); I != E; ++I) {
unsigned Reg = I->getReg();
const TargetRegisterClass *RC = I->getRegClass();
const TargetRegisterClass *RC = RegInfo->getMinimalPhysRegClass(Reg);
int FrameIdx;
if (RegInfo->hasReservedSpillSlot(Fn, Reg, FrameIdx)) {
@ -299,8 +298,10 @@ void PEI::insertCSRSpillsAndRestores(MachineFunction &Fn) {
EntryBlock->addLiveIn(CSI[i].getReg());
// Insert the spill to the stack frame.
TII.storeRegToStackSlot(*EntryBlock, I, CSI[i].getReg(), true,
CSI[i].getFrameIdx(), CSI[i].getRegClass(),TRI);
unsigned Reg = CSI[i].getReg();
const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
TII.storeRegToStackSlot(*EntryBlock, I, Reg, true,
CSI[i].getFrameIdx(), RC, TRI);
}
}
@ -324,9 +325,11 @@ void PEI::insertCSRSpillsAndRestores(MachineFunction &Fn) {
// terminators that preceed it.
if (!TII.restoreCalleeSavedRegisters(*MBB, I, CSI, TRI)) {
for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
TII.loadRegFromStackSlot(*MBB, I, CSI[i].getReg(),
unsigned Reg = CSI[i].getReg();
const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
TII.loadRegFromStackSlot(*MBB, I, Reg,
CSI[i].getFrameIdx(),
CSI[i].getRegClass(), TRI);
RC, TRI);
assert(I != MBB->begin() &&
"loadRegFromStackSlot didn't insert any code!");
// Insert in reverse order. loadRegFromStackSlot can insert
@ -370,10 +373,12 @@ void PEI::insertCSRSpillsAndRestores(MachineFunction &Fn) {
MBB->addLiveIn(blockCSI[i].getReg());
// Insert the spill to the stack frame.
TII.storeRegToStackSlot(*MBB, I, blockCSI[i].getReg(),
unsigned Reg = blockCSI[i].getReg();
const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
TII.storeRegToStackSlot(*MBB, I, Reg,
true,
blockCSI[i].getFrameIdx(),
blockCSI[i].getRegClass(), TRI);
RC, TRI);
}
}
@ -419,9 +424,11 @@ void PEI::insertCSRSpillsAndRestores(MachineFunction &Fn) {
// Restore all registers immediately before the return and any
// terminators that preceed it.
for (unsigned i = 0, e = blockCSI.size(); i != e; ++i) {
TII.loadRegFromStackSlot(*MBB, I, blockCSI[i].getReg(),
unsigned Reg = blockCSI[i].getReg();
const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
TII.loadRegFromStackSlot(*MBB, I, Reg,
blockCSI[i].getFrameIdx(),
blockCSI[i].getRegClass(), TRI);
RC, TRI);
assert(I != MBB->begin() &&
"loadRegFromStackSlot didn't insert any code!");
// Insert in reverse order. loadRegFromStackSlot can insert

3
lib/Target/ARM/ARMBaseInstrInfo.cpp
View File

@ -227,8 +227,9 @@ ARMBaseInstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
// Insert the spill to the stack frame. The register is killed at the spill
//
const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
storeRegToStackSlot(MBB, MI, Reg, isKill,
CSI[i].getFrameIdx(), CSI[i].getRegClass(), TRI);
CSI[i].getFrameIdx(), RC, TRI);
}
return true;
}

5
lib/Target/MBlaze/AsmPrinter/MBlazeAsmPrinter.cpp
View File

@ -145,8 +145,9 @@ void MBlazeAsmPrinter::printSavedRegsBitmask(raw_ostream &O) {
const MachineFrameInfo *MFI = MF->getFrameInfo();
const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
unsigned RegNum = MBlazeRegisterInfo::getRegisterNumbering(CSI[i].getReg());
if (CSI[i].getRegClass() == MBlaze::CPURegsRegisterClass)
unsigned Reg = CSI[i].getReg();
unsigned RegNum = MBlazeRegisterInfo::getRegisterNumbering(Reg);
if (MBlaze::CPURegsRegisterClass->contains(Reg))
CPUBitmask |= (1 << RegNum);
}

5
lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp
View File

@ -133,8 +133,9 @@ void MipsAsmPrinter::printSavedRegsBitmask(raw_ostream &O) {
const MachineFrameInfo *MFI = MF->getFrameInfo();
const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
unsigned RegNum = MipsRegisterInfo::getRegisterNumbering(CSI[i].getReg());
if (CSI[i].getRegClass() == Mips::CPURegsRegisterClass)
unsigned Reg = CSI[i].getReg();
unsigned RegNum = MipsRegisterInfo::getRegisterNumbering(Reg);
if (Mips::CPURegsRegisterClass->contains(Reg))
CPUBitmask |= (1 << RegNum);
else
FPUBitmask |= (1 << RegNum);

7
lib/Target/Mips/MipsRegisterInfo.cpp
View File

@ -251,7 +251,8 @@ void MipsRegisterInfo::adjustMipsStackFrame(MachineFunction &MF) const
StackOffset = ((StackOffset+StackAlign-1)/StackAlign*StackAlign);
for (unsigned i = 0, e = CSI.size(); i != e ; ++i) {
if (CSI[i].getRegClass() != Mips::CPURegsRegisterClass)
unsigned Reg = CSI[i].getReg();
if (!Mips::CPURegsRegisterClass->contains(Reg))
break;
MFI->setObjectOffset(CSI[i].getFrameIdx(), StackOffset);
TopCPUSavedRegOff = StackOffset;
@ -283,7 +284,8 @@ void MipsRegisterInfo::adjustMipsStackFrame(MachineFunction &MF) const
// Adjust FPU Callee Saved Registers Area. This Area must be
// aligned to the default Stack Alignment requirements.
for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
if (CSI[i].getRegClass() == Mips::CPURegsRegisterClass)
unsigned Reg = CSI[i].getReg();
if (Mips::CPURegsRegisterClass->contains(Reg))
continue;
MFI->setObjectOffset(CSI[i].getFrameIdx(), StackOffset);
TopFPUSavedRegOff = StackOffset;
@ -500,4 +502,3 @@ getDwarfRegNum(unsigned RegNum, bool isEH) const {
}
#include "MipsGenRegisterInfo.inc"

26
lib/Target/PowerPC/PPCRegisterInfo.cpp
View File

@ -993,9 +993,7 @@ PPCRegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF)
for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
unsigned Reg = CSI[i].getReg();
const TargetRegisterClass *RC = CSI[i].getRegClass();
if (RC == PPC::GPRCRegisterClass) {
if (PPC::GPRCRegisterClass->contains(Reg)) {
HasGPSaveArea = true;
GPRegs.push_back(CSI[i]);
@ -1003,7 +1001,7 @@ PPCRegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF)
if (Reg < MinGPR) {
MinGPR = Reg;
}
} else if (RC == PPC::G8RCRegisterClass) {
} else if (PPC::G8RCRegisterClass->contains(Reg)) {
HasG8SaveArea = true;
G8Regs.push_back(CSI[i]);
@ -1011,7 +1009,7 @@ PPCRegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF)
if (Reg < MinG8R) {
MinG8R = Reg;
}
} else if (RC == PPC::F8RCRegisterClass) {
} else if (PPC::F8RCRegisterClass->contains(Reg)) {
HasFPSaveArea = true;
FPRegs.push_back(CSI[i]);
@ -1020,12 +1018,12 @@ PPCRegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF)
MinFPR = Reg;
}
// FIXME SVR4: Disable CR save area for now.
} else if ( RC == PPC::CRBITRCRegisterClass
|| RC == PPC::CRRCRegisterClass) {
} else if (PPC::CRBITRCRegisterClass->contains(Reg)
|| PPC::CRRCRegisterClass->contains(Reg)) {
// HasCRSaveArea = true;
} else if (RC == PPC::VRSAVERCRegisterClass) {
} else if (PPC::VRSAVERCRegisterClass->contains(Reg)) {
HasVRSAVESaveArea = true;
} else if (RC == PPC::VRRCRegisterClass) {
} else if (PPC::VRRCRegisterClass->contains(Reg)) {
HasVRSaveArea = true;
VRegs.push_back(CSI[i]);
@ -1106,9 +1104,10 @@ PPCRegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF)
// which have the CR/CRBIT register class?
// Adjust the frame index of the CR spill slot.
for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
const TargetRegisterClass *RC = CSI[i].getRegClass();
unsigned Reg = CSI[i].getReg();
if (RC == PPC::CRBITRCRegisterClass || RC == PPC::CRRCRegisterClass) {
if (PPC::CRBITRCRegisterClass->contains(Reg) ||
PPC::CRRCRegisterClass->contains(Reg)) {
int FI = CSI[i].getFrameIdx();
FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
@ -1123,9 +1122,9 @@ PPCRegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF)
// which have the VRSAVE register class?
// Adjust the frame index of the VRSAVE spill slot.
for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
const TargetRegisterClass *RC = CSI[i].getRegClass();
unsigned Reg = CSI[i].getReg();
if (RC == PPC::VRSAVERCRegisterClass) {
if (PPC::VRSAVERCRegisterClass->contains(Reg)) {
int FI = CSI[i].getFrameIdx();
FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
@ -1628,4 +1627,3 @@ int PPCRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
}
#include "PPCGenRegisterInfo.inc"

16
lib/Target/SystemZ/SystemZInstrInfo.cpp
View File

@ -286,8 +286,7 @@ SystemZInstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
unsigned LowReg = 0, HighReg = 0, StartOffset = -1U, EndOffset = 0;
for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
unsigned Reg = CSI[i].getReg();
const TargetRegisterClass *RegClass = CSI[i].getRegClass();
if (RegClass != &SystemZ::FP64RegClass) {
if (!SystemZ::FP64RegClass.contains(Reg)) {
unsigned Offset = RegSpillOffsets[Reg];
CalleeFrameSize += 8;
if (StartOffset > Offset) {
@ -332,11 +331,10 @@ SystemZInstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
// Save FPRs
for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
unsigned Reg = CSI[i].getReg();
const TargetRegisterClass *RegClass = CSI[i].getRegClass();
if (RegClass == &SystemZ::FP64RegClass) {
if (SystemZ::FP64RegClass.contains(Reg)) {
MBB.addLiveIn(Reg);
storeRegToStackSlot(MBB, MI, Reg, true, CSI[i].getFrameIdx(), RegClass,
&RI);
storeRegToStackSlot(MBB, MI, Reg, true, CSI[i].getFrameIdx(),
&SystemZ::FP64RegClass, &RI);
}
}
@ -361,9 +359,9 @@ SystemZInstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
// Restore FP registers
for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
unsigned Reg = CSI[i].getReg();
const TargetRegisterClass *RegClass = CSI[i].getRegClass();
if (RegClass == &SystemZ::FP64RegClass)
loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(), RegClass, &RI);
if (SystemZ::FP64RegClass.contains(Reg))
loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(),
&SystemZ::FP64RegClass, &RI);
}
// Restore GP registers

14
lib/Target/X86/X86InstrInfo.cpp
View File

@ -2277,18 +2277,17 @@ bool X86InstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
unsigned Opc = is64Bit ? X86::PUSH64r : X86::PUSH32r;
for (unsigned i = CSI.size(); i != 0; --i) {
unsigned Reg = CSI[i-1].getReg();
const TargetRegisterClass *RegClass = CSI[i-1].getRegClass();
// Add the callee-saved register as live-in. It's killed at the spill.
MBB.addLiveIn(Reg);
if (Reg == FPReg)
// X86RegisterInfo::emitPrologue will handle spilling of frame register.
continue;
if (RegClass != &X86::VR128RegClass && !isWin64) {
if (!X86::VR128RegClass.contains(Reg) && !isWin64) {
CalleeFrameSize += SlotSize;
BuildMI(MBB, MI, DL, get(Opc)).addReg(Reg, RegState::Kill);
} else {
storeRegToStackSlot(MBB, MI, Reg, true, CSI[i-1].getFrameIdx(), RegClass,
&RI);
storeRegToStackSlot(MBB, MI, Reg, true, CSI[i-1].getFrameIdx(),
&X86::VR128RegClass, &RI);
}
}
@ -2315,11 +2314,11 @@ bool X86InstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
if (Reg == FPReg)
// X86RegisterInfo::emitEpilogue will handle restoring of frame register.
continue;
const TargetRegisterClass *RegClass = CSI[i].getRegClass();
if (RegClass != &X86::VR128RegClass && !isWin64) {
if (!X86::VR128RegClass.contains(Reg) && !isWin64) {
BuildMI(MBB, MI, DL, get(Opc), Reg);
} else {
loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(), RegClass, &RI);
loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(),
&X86::VR128RegClass, &RI);
}
}
return true;
@ -3783,4 +3782,3 @@ void X86InstrInfo::SetSSEDomain(MachineInstr *MI, unsigned Domain) const {
void X86InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
NopInst.setOpcode(X86::NOOP);
}

11
lib/Target/XCore/XCoreInstrInfo.cpp
View File

@ -438,8 +438,10 @@ bool XCoreInstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
// Add the callee-saved register as live-in. It's killed at the spill.
MBB.addLiveIn(it->getReg());
storeRegToStackSlot(MBB, MI, it->getReg(), true,
it->getFrameIdx(), it->getRegClass(), &RI);
unsigned Reg = it->getReg();
const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
storeRegToStackSlot(MBB, MI, Reg, true,
it->getFrameIdx(), RC, &RI);
if (emitFrameMoves) {
MCSymbol *SaveLabel = MF->getContext().CreateTempSymbol();
BuildMI(MBB, MI, DL, get(XCore::DBG_LABEL)).addSym(SaveLabel);
@ -460,10 +462,11 @@ bool XCoreInstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
--BeforeI;
for (std::vector<CalleeSavedInfo>::const_iterator it = CSI.begin();
it != CSI.end(); ++it) {
unsigned Reg = it->getReg();
const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
loadRegFromStackSlot(MBB, MI, it->getReg(),
it->getFrameIdx(),
it->getRegClass(), &RI);
RC, &RI);
assert(MI != MBB.begin() &&
"loadRegFromStackSlot didn't insert any code!");
// Insert in reverse order. loadRegFromStackSlot can insert multiple