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Switch BCC, MOVCCr, etc. to PredicateOperand.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36948 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
2007-05-08 21:08:43 +00:00
parent f88b3a5698
commit 42d712b306
4 changed files with 22 additions and 17 deletions
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4
lib/Target/ARM/ARMAsmPrinter.cpp
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@@ -101,7 +101,7 @@ namespace {
void printThumbAddrModeS2Operand(const MachineInstr *MI, int OpNo); void printThumbAddrModeS2Operand(const MachineInstr *MI, int OpNo);
void printThumbAddrModeS4Operand(const MachineInstr *MI, int OpNo); void printThumbAddrModeS4Operand(const MachineInstr *MI, int OpNo);
void printThumbAddrModeSPOperand(const MachineInstr *MI, int OpNo); void printThumbAddrModeSPOperand(const MachineInstr *MI, int OpNo);
void printCCOperand(const MachineInstr *MI, int opNum); void printPredicateOperand(const MachineInstr *MI, int opNum);
void printPCLabel(const MachineInstr *MI, int opNum); void printPCLabel(const MachineInstr *MI, int opNum);
void printRegisterList(const MachineInstr *MI, int opNum); void printRegisterList(const MachineInstr *MI, int opNum);
void printCPInstOperand(const MachineInstr *MI, int opNum, void printCPInstOperand(const MachineInstr *MI, int opNum,
@@ -613,7 +613,7 @@ void ARMAsmPrinter::printThumbAddrModeSPOperand(const MachineInstr *MI,int Op) {
O << "]"; O << "]";
} }
void ARMAsmPrinter::printCCOperand(const MachineInstr *MI, int opNum) { void ARMAsmPrinter::printPredicateOperand(const MachineInstr *MI, int opNum) {
int CC = (int)MI->getOperand(opNum).getImmedValue(); int CC = (int)MI->getOperand(opNum).getImmedValue();
O << ARMCondCodeToString((ARMCC::CondCodes)CC); O << ARMCondCodeToString((ARMCC::CondCodes)CC);
} }

23
lib/Target/ARM/ARMInstrInfo.td
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@@ -162,11 +162,6 @@ def sext_16_node : PatLeaf<(i32 GPR:$a), [{
// Branch target. // Branch target.
def brtarget : Operand<OtherVT>; def brtarget : Operand<OtherVT>;
// Operand for printing out a condition code.
def CCOp : Operand<i32> {
let PrintMethod = "printCCOperand";
}
// A list of registers separated by comma. Used by load/store multiple. // A list of registers separated by comma. Used by load/store multiple.
def reglist : Operand<i32> { def reglist : Operand<i32> {
let PrintMethod = "printRegisterList"; let PrintMethod = "printRegisterList";
@@ -282,6 +277,16 @@ def addrmodepc : Operand<i32>,
let MIOperandInfo = (ops GPR, i32imm); let MIOperandInfo = (ops GPR, i32imm);
} }
// ARM branch / cmov condition code operand.
def ccop : PredicateOperand<i32, (ops i32imm), (ops)> {
let PrintMethod = "printPredicateOperand";
}
// ARM Predicate operand. Default to 14 = always (AL).
def pred : PredicateOperand<i32, (ops i32imm), (ops (i32 14))> {
let PrintMethod = "printPredicateOperand";
}
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// ARM Instruction flags. These need to match ARMInstrInfo.h. // ARM Instruction flags. These need to match ARMInstrInfo.h.
// //
@@ -579,7 +584,7 @@ let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
} }
let isBranch = 1, isTerminator = 1, noResults = 1, isBarrier = 1 in let isBranch = 1, isTerminator = 1, noResults = 1, isBarrier = 1 in
def Bcc : AI<(ops brtarget:$dst, CCOp:$cc), "b$cc $dst", def Bcc : AI<(ops brtarget:$dst, ccop:$cc), "b$cc $dst",
[(ARMbrcond bb:$dst, imm:$cc)]>; [(ARMbrcond bb:$dst, imm:$cc)]>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
@@ -1041,17 +1046,17 @@ def : ARMPat<(ARMcmpNZ GPR:$src, so_imm_neg:$imm),
// Conditional moves // Conditional moves
def MOVCCr : AI<(ops GPR:$dst, GPR:$false, GPR:$true, CCOp:$cc), def MOVCCr : AI<(ops GPR:$dst, GPR:$false, GPR:$true, ccop:$cc),
"mov$cc $dst, $true", "mov$cc $dst, $true",
[(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc))]>, [(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc))]>,
RegConstraint<"$false = $dst">; RegConstraint<"$false = $dst">;
def MOVCCs : AI<(ops GPR:$dst, GPR:$false, so_reg:$true, CCOp:$cc), def MOVCCs : AI<(ops GPR:$dst, GPR:$false, so_reg:$true, ccop:$cc),
"mov$cc $dst, $true", "mov$cc $dst, $true",
[(set GPR:$dst, (ARMcmov GPR:$false, so_reg:$true,imm:$cc))]>, [(set GPR:$dst, (ARMcmov GPR:$false, so_reg:$true,imm:$cc))]>,
RegConstraint<"$false = $dst">; RegConstraint<"$false = $dst">;
def MOVCCi : AI<(ops GPR:$dst, GPR:$false, so_imm:$true, CCOp:$cc), def MOVCCi : AI<(ops GPR:$dst, GPR:$false, so_imm:$true, ccop:$cc),
"mov$cc $dst, $true", "mov$cc $dst, $true",
[(set GPR:$dst, (ARMcmov GPR:$false, so_imm:$true,imm:$cc))]>, [(set GPR:$dst, (ARMcmov GPR:$false, so_imm:$true,imm:$cc))]>,
RegConstraint<"$false = $dst">; RegConstraint<"$false = $dst">;

4
lib/Target/ARM/ARMInstrThumb.td
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@@ -207,7 +207,7 @@ let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
} }
let isBranch = 1, isTerminator = 1, noResults = 1, isBarrier = 1 in let isBranch = 1, isTerminator = 1, noResults = 1, isBarrier = 1 in
def tBcc : TI<(ops brtarget:$dst, CCOp:$cc), "b$cc $dst", def tBcc : TI<(ops brtarget:$dst, ccop:$cc), "b$cc $dst",
[(ARMbrcond bb:$dst, imm:$cc)]>; [(ARMbrcond bb:$dst, imm:$cc)]>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
@@ -503,7 +503,7 @@ def tUXTH : TI<(ops GPR:$dst, GPR:$src),
// Expanded by the scheduler into a branch sequence. // Expanded by the scheduler into a branch sequence.
let usesCustomDAGSchedInserter = 1 in // Expanded by the scheduler. let usesCustomDAGSchedInserter = 1 in // Expanded by the scheduler.
def tMOVCCr : def tMOVCCr :
PseudoInst<(ops GPR:$dst, GPR:$false, GPR:$true, CCOp:$cc), PseudoInst<(ops GPR:$dst, GPR:$false, GPR:$true, ccop:$cc),
"@ tMOVCCr $cc", "@ tMOVCCr $cc",
[(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc))]>; [(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc))]>;

8
lib/Target/ARM/ARMInstrVFP.td
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@@ -344,22 +344,22 @@ def FNMSCS : ASI<(ops SPR:$dst, SPR:$dstin, SPR:$a, SPR:$b),
// FP Conditional moves. // FP Conditional moves.
// //
def FCPYDcc : ADI<(ops DPR:$dst, DPR:$false, DPR:$true, CCOp:$cc), def FCPYDcc : ADI<(ops DPR:$dst, DPR:$false, DPR:$true, ccop:$cc),
"fcpyd$cc $dst, $true", "fcpyd$cc $dst, $true",
[(set DPR:$dst, (ARMcmov DPR:$false, DPR:$true, imm:$cc))]>, [(set DPR:$dst, (ARMcmov DPR:$false, DPR:$true, imm:$cc))]>,
RegConstraint<"$false = $dst">; RegConstraint<"$false = $dst">;
def FCPYScc : ASI<(ops SPR:$dst, SPR:$false, SPR:$true, CCOp:$cc), def FCPYScc : ASI<(ops SPR:$dst, SPR:$false, SPR:$true, ccop:$cc),
"fcpys$cc $dst, $true", "fcpys$cc $dst, $true",
[(set SPR:$dst, (ARMcmov SPR:$false, SPR:$true, imm:$cc))]>, [(set SPR:$dst, (ARMcmov SPR:$false, SPR:$true, imm:$cc))]>,
RegConstraint<"$false = $dst">; RegConstraint<"$false = $dst">;
def FNEGDcc : ADI<(ops DPR:$dst, DPR:$false, DPR:$true, CCOp:$cc), def FNEGDcc : ADI<(ops DPR:$dst, DPR:$false, DPR:$true, ccop:$cc),
"fnegd$cc $dst, $true", "fnegd$cc $dst, $true",
[(set DPR:$dst, (ARMcneg DPR:$false, DPR:$true, imm:$cc))]>, [(set DPR:$dst, (ARMcneg DPR:$false, DPR:$true, imm:$cc))]>,
RegConstraint<"$false = $dst">; RegConstraint<"$false = $dst">;
def FNEGScc : ASI<(ops SPR:$dst, SPR:$false, SPR:$true, CCOp:$cc), def FNEGScc : ASI<(ops SPR:$dst, SPR:$false, SPR:$true, ccop:$cc),
"fnegs$cc $dst, $true", "fnegs$cc $dst, $true",
[(set SPR:$dst, (ARMcneg SPR:$false, SPR:$true, imm:$cc))]>, [(set SPR:$dst, (ARMcneg SPR:$false, SPR:$true, imm:$cc))]>,
RegConstraint<"$false = $dst">; RegConstraint<"$false = $dst">;