6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-07-25 13:24:46 +00:00
Code Issues Projects Releases Wiki Activity

Add support for the X86 secure guard extensions instructions in assembler (SGX).

Browse Source 
This allows assembling the two new instructions, encls and enclu for the
SKX processor model.

Note the diffs are a bigger than what might think, but to fit the new
MRM_CF and MRM_D7 in things in the right places things had to be
renumbered and shuffled down causing a bit more diffs.

rdar://16228228


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214460 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Kevin Enderby
2014-07-31 23:57:38 +00:00
parent 0b3444cca9
commit 42deb12738
11 changed files with 178 additions and 124 deletions
Download Patch File Download Diff File Expand all files Collapse all files

52
lib/Target/X86/MCTargetDesc/X86BaseInfo.h
View File

@@ -303,17 +303,18 @@ namespace X86II {
//// MRM_XX - A mod/rm byte of exactly 0xXX. //// MRM_XX - A mod/rm byte of exactly 0xXX.
MRM_C0 = 32, MRM_C1 = 33, MRM_C2 = 34, MRM_C3 = 35, MRM_C0 = 32, MRM_C1 = 33, MRM_C2 = 34, MRM_C3 = 35,
MRM_C4 = 36, MRM_C8 = 37, MRM_C9 = 38, MRM_CA = 39, MRM_C4 = 36, MRM_C8 = 37, MRM_C9 = 38, MRM_CA = 39,
MRM_CB = 40, MRM_D0 = 41, MRM_D1 = 42, MRM_D4 = 43, MRM_CB = 40, MRM_CF = 41, MRM_D0 = 42, MRM_D1 = 43,
MRM_D5 = 44, MRM_D6 = 45, MRM_D8 = 46, MRM_D9 = 47, MRM_D4 = 44, MRM_D5 = 45, MRM_D6 = 46, MRM_D7 = 47,
MRM_DA = 48, MRM_DB = 49, MRM_DC = 50, MRM_DD = 51, MRM_D8 = 48, MRM_D9 = 49, MRM_DA = 50, MRM_DB = 51,
MRM_DE = 52, MRM_DF = 53, MRM_E0 = 54, MRM_E1 = 55, MRM_DC = 52, MRM_DD = 53, MRM_DE = 54, MRM_DF = 55,
MRM_E2 = 56, MRM_E3 = 57, MRM_E4 = 58, MRM_E5 = 59, MRM_E0 = 56, MRM_E1 = 57, MRM_E2 = 58, MRM_E3 = 59,
MRM_E8 = 60, MRM_E9 = 61, MRM_EA = 62, MRM_EB = 63, MRM_E4 = 60, MRM_E5 = 61, MRM_E8 = 62, MRM_E9 = 63,
MRM_EC = 64, MRM_ED = 65, MRM_EE = 66, MRM_F0 = 67, MRM_EA = 64, MRM_EB = 65, MRM_EC = 66, MRM_ED = 67,
MRM_F1 = 68, MRM_F2 = 69, MRM_F3 = 70, MRM_F4 = 71, MRM_EE = 68, MRM_F0 = 69, MRM_F1 = 70, MRM_F2 = 71,
MRM_F5 = 72, MRM_F6 = 73, MRM_F7 = 74, MRM_F8 = 75, MRM_F3 = 72, MRM_F4 = 73, MRM_F5 = 74, MRM_F6 = 75,
MRM_F9 = 76, MRM_FA = 77, MRM_FB = 78, MRM_FC = 79, MRM_F7 = 76, MRM_F8 = 77, MRM_F9 = 78, MRM_FA = 79,
MRM_FD = 80, MRM_FE = 81, MRM_FF = 82, MRM_FB = 80, MRM_FC = 81, MRM_FD = 82, MRM_FE = 83,
MRM_FF = 84,
FormMask = 127, FormMask = 127,
@@ -697,20 +698,21 @@ namespace X86II {
case X86II::MRM_C0: case X86II::MRM_C1: case X86II::MRM_C2: case X86II::MRM_C0: case X86II::MRM_C1: case X86II::MRM_C2:
case X86II::MRM_C3: case X86II::MRM_C4: case X86II::MRM_C8: case X86II::MRM_C3: case X86II::MRM_C4: case X86II::MRM_C8:
case X86II::MRM_C9: case X86II::MRM_CA: case X86II::MRM_CB: case X86II::MRM_C9: case X86II::MRM_CA: case X86II::MRM_CB:
case X86II::MRM_D0: case X86II::MRM_D1: case X86II::MRM_D4: case X86II::MRM_CF: case X86II::MRM_D0: case X86II::MRM_D1:
case X86II::MRM_D5: case X86II::MRM_D6: case X86II::MRM_D8: case X86II::MRM_D4: case X86II::MRM_D5: case X86II::MRM_D6:
case X86II::MRM_D9: case X86II::MRM_DA: case X86II::MRM_DB: case X86II::MRM_D7: case X86II::MRM_D8: case X86II::MRM_D9:
case X86II::MRM_DC: case X86II::MRM_DD: case X86II::MRM_DE: case X86II::MRM_DA: case X86II::MRM_DB: case X86II::MRM_DC:
case X86II::MRM_DF: case X86II::MRM_E0: case X86II::MRM_E1: case X86II::MRM_DD: case X86II::MRM_DE: case X86II::MRM_DF:
case X86II::MRM_E2: case X86II::MRM_E3: case X86II::MRM_E4: case X86II::MRM_E0: case X86II::MRM_E1: case X86II::MRM_E2:
case X86II::MRM_E5: case X86II::MRM_E8: case X86II::MRM_E9: case X86II::MRM_E3: case X86II::MRM_E4: case X86II::MRM_E5:
case X86II::MRM_EA: case X86II::MRM_EB: case X86II::MRM_EC: case X86II::MRM_E8: case X86II::MRM_E9: case X86II::MRM_EA:
case X86II::MRM_ED: case X86II::MRM_EE: case X86II::MRM_F0: case X86II::MRM_EB: case X86II::MRM_EC: case X86II::MRM_ED:
case X86II::MRM_F1: case X86II::MRM_F2: case X86II::MRM_F3: case X86II::MRM_EE: case X86II::MRM_F0: case X86II::MRM_F1:
case X86II::MRM_F4: case X86II::MRM_F5: case X86II::MRM_F6: case X86II::MRM_F2: case X86II::MRM_F3: case X86II::MRM_F4:
case X86II::MRM_F7: case X86II::MRM_F8: case X86II::MRM_F9: case X86II::MRM_F5: case X86II::MRM_F6: case X86II::MRM_F7:
case X86II::MRM_FA: case X86II::MRM_FB: case X86II::MRM_FC: case X86II::MRM_F8: case X86II::MRM_F9: case X86II::MRM_FA:
case X86II::MRM_FD: case X86II::MRM_FE: case X86II::MRM_FF: case X86II::MRM_FB: case X86II::MRM_FC: case X86II::MRM_FD:
case X86II::MRM_FE: case X86II::MRM_FF:
return -1; return -1;
} }
} }

31
lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
View File

@@ -1437,20 +1437,21 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS,
case X86II::MRM_C0: case X86II::MRM_C1: case X86II::MRM_C2: case X86II::MRM_C0: case X86II::MRM_C1: case X86II::MRM_C2:
case X86II::MRM_C3: case X86II::MRM_C4: case X86II::MRM_C8: case X86II::MRM_C3: case X86II::MRM_C4: case X86II::MRM_C8:
case X86II::MRM_C9: case X86II::MRM_CA: case X86II::MRM_CB: case X86II::MRM_C9: case X86II::MRM_CA: case X86II::MRM_CB:
case X86II::MRM_D0: case X86II::MRM_D1: case X86II::MRM_D4: case X86II::MRM_CF: case X86II::MRM_D0: case X86II::MRM_D1:
case X86II::MRM_D5: case X86II::MRM_D6: case X86II::MRM_D8: case X86II::MRM_D4: case X86II::MRM_D5: case X86II::MRM_D6:
case X86II::MRM_D9: case X86II::MRM_DA: case X86II::MRM_DB: case X86II::MRM_D7: case X86II::MRM_D8: case X86II::MRM_D9:
case X86II::MRM_DC: case X86II::MRM_DD: case X86II::MRM_DE: case X86II::MRM_DA: case X86II::MRM_DB: case X86II::MRM_DC:
case X86II::MRM_DF: case X86II::MRM_E0: case X86II::MRM_E1: case X86II::MRM_DD: case X86II::MRM_DE: case X86II::MRM_DF:
case X86II::MRM_E2: case X86II::MRM_E3: case X86II::MRM_E4: case X86II::MRM_E0: case X86II::MRM_E1: case X86II::MRM_E2:
case X86II::MRM_E5: case X86II::MRM_E8: case X86II::MRM_E9: case X86II::MRM_E3: case X86II::MRM_E4: case X86II::MRM_E5:
case X86II::MRM_EA: case X86II::MRM_EB: case X86II::MRM_EC: case X86II::MRM_E8: case X86II::MRM_E9: case X86II::MRM_EA:
case X86II::MRM_ED: case X86II::MRM_EE: case X86II::MRM_F0: case X86II::MRM_EB: case X86II::MRM_EC: case X86II::MRM_ED:
case X86II::MRM_F1: case X86II::MRM_F2: case X86II::MRM_F3: case X86II::MRM_EE: case X86II::MRM_F0: case X86II::MRM_F1:
case X86II::MRM_F4: case X86II::MRM_F5: case X86II::MRM_F6: case X86II::MRM_F2: case X86II::MRM_F3: case X86II::MRM_F4:
case X86II::MRM_F7: case X86II::MRM_F8: case X86II::MRM_F9: case X86II::MRM_F5: case X86II::MRM_F6: case X86II::MRM_F7:
case X86II::MRM_FA: case X86II::MRM_FB: case X86II::MRM_FC: case X86II::MRM_F8: case X86II::MRM_F9: case X86II::MRM_FA:
case X86II::MRM_FD: case X86II::MRM_FE: case X86II::MRM_FF: case X86II::MRM_FB: case X86II::MRM_FC: case X86II::MRM_FD:
case X86II::MRM_FE: case X86II::MRM_FF:
EmitByte(BaseOpcode, CurByte, OS); EmitByte(BaseOpcode, CurByte, OS);
unsigned char MRM; unsigned char MRM;
@@ -1465,11 +1466,13 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS,
case X86II::MRM_C9: MRM = 0xC9; break; case X86II::MRM_C9: MRM = 0xC9; break;
case X86II::MRM_CA: MRM = 0xCA; break; case X86II::MRM_CA: MRM = 0xCA; break;
case X86II::MRM_CB: MRM = 0xCB; break; case X86II::MRM_CB: MRM = 0xCB; break;
case X86II::MRM_CF: MRM = 0xCF; break;
case X86II::MRM_D0: MRM = 0xD0; break; case X86II::MRM_D0: MRM = 0xD0; break;
case X86II::MRM_D1: MRM = 0xD1; break; case X86II::MRM_D1: MRM = 0xD1; break;
case X86II::MRM_D4: MRM = 0xD4; break; case X86II::MRM_D4: MRM = 0xD4; break;
case X86II::MRM_D5: MRM = 0xD5; break; case X86II::MRM_D5: MRM = 0xD5; break;
case X86II::MRM_D6: MRM = 0xD6; break; case X86II::MRM_D6: MRM = 0xD6; break;
case X86II::MRM_D7: MRM = 0xD7; break;
case X86II::MRM_D8: MRM = 0xD8; break; case X86II::MRM_D8: MRM = 0xD8; break;
case X86II::MRM_D9: MRM = 0xD9; break; case X86II::MRM_D9: MRM = 0xD9; break;
case X86II::MRM_DA: MRM = 0xDA; break; case X86II::MRM_DA: MRM = 0xDA; break;

4
lib/Target/X86/X86.td
View File

@@ -157,6 +157,8 @@ def FeatureADX : SubtargetFeature<"adx", "HasADX", "true",
def FeatureSHA : SubtargetFeature<"sha", "HasSHA", "true", def FeatureSHA : SubtargetFeature<"sha", "HasSHA", "true",
"Enable SHA instructions", "Enable SHA instructions",
[FeatureSSE2]>; [FeatureSSE2]>;
def FeatureSGX : SubtargetFeature<"sgx", "HasSGX", "true",
"Support SGX instructions">;
def FeaturePRFCHW : SubtargetFeature<"prfchw", "HasPRFCHW", "true", def FeaturePRFCHW : SubtargetFeature<"prfchw", "HasPRFCHW", "true",
"Support PRFCHW instructions">; "Support PRFCHW instructions">;
def FeatureRDSEED : SubtargetFeature<"rdseed", "HasRDSEED", "true", def FeatureRDSEED : SubtargetFeature<"rdseed", "HasRDSEED", "true",
@@ -293,7 +295,7 @@ def : ProcessorModel<"skx", HaswellModel,
FeatureAES, FeaturePCLMUL, FeatureRDRAND, FeatureF16C, FeatureAES, FeaturePCLMUL, FeatureRDRAND, FeatureF16C,
FeatureFSGSBase, FeatureMOVBE, FeatureLZCNT, FeatureBMI, FeatureFSGSBase, FeatureMOVBE, FeatureLZCNT, FeatureBMI,
FeatureBMI2, FeatureFMA, FeatureRTM, FeatureHLE, FeatureBMI2, FeatureFMA, FeatureRTM, FeatureHLE,
FeatureSlowIncDec]>; FeatureSlowIncDec, FeatureSGX]>;
def : Proc<"k6", [FeatureMMX]>; def : Proc<"k6", [FeatureMMX]>;
def : Proc<"k6-2", [Feature3DNow]>; def : Proc<"k6-2", [Feature3DNow]>;

31
lib/Target/X86/X86CodeEmitter.cpp
View File

@@ -1385,20 +1385,21 @@ void Emitter<CodeEmitter>::emitInstruction(MachineInstr &MI,
case X86II::MRM_C0: case X86II::MRM_C1: case X86II::MRM_C2: case X86II::MRM_C0: case X86II::MRM_C1: case X86II::MRM_C2:
case X86II::MRM_C3: case X86II::MRM_C4: case X86II::MRM_C8: case X86II::MRM_C3: case X86II::MRM_C4: case X86II::MRM_C8:
case X86II::MRM_C9: case X86II::MRM_CA: case X86II::MRM_CB: case X86II::MRM_C9: case X86II::MRM_CA: case X86II::MRM_CB:
case X86II::MRM_D0: case X86II::MRM_D1: case X86II::MRM_D4: case X86II::MRM_CF: case X86II::MRM_D0: case X86II::MRM_D1:
case X86II::MRM_D5: case X86II::MRM_D6: case X86II::MRM_D8: case X86II::MRM_D4: case X86II::MRM_D5: case X86II::MRM_D6:
case X86II::MRM_D9: case X86II::MRM_DA: case X86II::MRM_DB: case X86II::MRM_D7: case X86II::MRM_D8: case X86II::MRM_D9:
case X86II::MRM_DC: case X86II::MRM_DD: case X86II::MRM_DE: case X86II::MRM_DA: case X86II::MRM_DB: case X86II::MRM_DC:
case X86II::MRM_DF: case X86II::MRM_E0: case X86II::MRM_E1: case X86II::MRM_DD: case X86II::MRM_DE: case X86II::MRM_DF:
case X86II::MRM_E2: case X86II::MRM_E3: case X86II::MRM_E4: case X86II::MRM_E0: case X86II::MRM_E1: case X86II::MRM_E2:
case X86II::MRM_E5: case X86II::MRM_E8: case X86II::MRM_E9: case X86II::MRM_E3: case X86II::MRM_E4: case X86II::MRM_E5:
case X86II::MRM_EA: case X86II::MRM_EB: case X86II::MRM_EC: case X86II::MRM_E8: case X86II::MRM_E9: case X86II::MRM_EA:
case X86II::MRM_ED: case X86II::MRM_EE: case X86II::MRM_F0: case X86II::MRM_EB: case X86II::MRM_EC: case X86II::MRM_ED:
case X86II::MRM_F1: case X86II::MRM_F2: case X86II::MRM_F3: case X86II::MRM_EE: case X86II::MRM_F0: case X86II::MRM_F1:
case X86II::MRM_F4: case X86II::MRM_F5: case X86II::MRM_F6: case X86II::MRM_F2: case X86II::MRM_F3: case X86II::MRM_F4:
case X86II::MRM_F7: case X86II::MRM_F8: case X86II::MRM_F9: case X86II::MRM_F5: case X86II::MRM_F6: case X86II::MRM_F7:
case X86II::MRM_FA: case X86II::MRM_FB: case X86II::MRM_FC: case X86II::MRM_F8: case X86II::MRM_F9: case X86II::MRM_FA:
case X86II::MRM_FD: case X86II::MRM_FE: case X86II::MRM_FF: case X86II::MRM_FB: case X86II::MRM_FC: case X86II::MRM_FD:
case X86II::MRM_FE: case X86II::MRM_FF:
MCE.emitByte(BaseOpcode); MCE.emitByte(BaseOpcode);
unsigned char MRM; unsigned char MRM;
@@ -1413,11 +1414,13 @@ void Emitter<CodeEmitter>::emitInstruction(MachineInstr &MI,
case X86II::MRM_C9: MRM = 0xC9; break; case X86II::MRM_C9: MRM = 0xC9; break;
case X86II::MRM_CA: MRM = 0xCA; break; case X86II::MRM_CA: MRM = 0xCA; break;
case X86II::MRM_CB: MRM = 0xCB; break; case X86II::MRM_CB: MRM = 0xCB; break;
case X86II::MRM_CF: MRM = 0xCF; break;
case X86II::MRM_D0: MRM = 0xD0; break; case X86II::MRM_D0: MRM = 0xD0; break;
case X86II::MRM_D1: MRM = 0xD1; break; case X86II::MRM_D1: MRM = 0xD1; break;
case X86II::MRM_D4: MRM = 0xD4; break; case X86II::MRM_D4: MRM = 0xD4; break;
case X86II::MRM_D5: MRM = 0xD5; break; case X86II::MRM_D5: MRM = 0xD5; break;
case X86II::MRM_D6: MRM = 0xD6; break; case X86II::MRM_D6: MRM = 0xD6; break;
case X86II::MRM_D7: MRM = 0xD7; break;
case X86II::MRM_D8: MRM = 0xD8; break; case X86II::MRM_D8: MRM = 0xD8; break;
case X86II::MRM_D9: MRM = 0xD9; break; case X86II::MRM_D9: MRM = 0xD9; break;
case X86II::MRM_DA: MRM = 0xDA; break; case X86II::MRM_DA: MRM = 0xDA; break;

29
lib/Target/X86/X86InstrFormats.td
View File

@@ -36,20 +36,21 @@ def MRM6m : Format<30>; def MRM7m : Format<31>;
def MRM_C0 : Format<32>; def MRM_C1 : Format<33>; def MRM_C2 : Format<34>; def MRM_C0 : Format<32>; def MRM_C1 : Format<33>; def MRM_C2 : Format<34>;
def MRM_C3 : Format<35>; def MRM_C4 : Format<36>; def MRM_C8 : Format<37>; def MRM_C3 : Format<35>; def MRM_C4 : Format<36>; def MRM_C8 : Format<37>;
def MRM_C9 : Format<38>; def MRM_CA : Format<39>; def MRM_CB : Format<40>; def MRM_C9 : Format<38>; def MRM_CA : Format<39>; def MRM_CB : Format<40>;
def MRM_D0 : Format<41>; def MRM_D1 : Format<42>; def MRM_D4 : Format<43>; def MRM_CF : Format<41>; def MRM_D0 : Format<42>; def MRM_D1 : Format<43>;
def MRM_D5 : Format<44>; def MRM_D6 : Format<45>; def MRM_D8 : Format<46>; def MRM_D4 : Format<44>; def MRM_D5 : Format<45>; def MRM_D6 : Format<46>;
def MRM_D9 : Format<47>; def MRM_DA : Format<48>; def MRM_DB : Format<49>; def MRM_D7 : Format<47>; def MRM_D8 : Format<48>; def MRM_D9 : Format<49>;
def MRM_DC : Format<50>; def MRM_DD : Format<51>; def MRM_DE : Format<52>; def MRM_DA : Format<50>; def MRM_DB : Format<51>; def MRM_DC : Format<52>;
def MRM_DF : Format<53>; def MRM_E0 : Format<54>; def MRM_E1 : Format<55>; def MRM_DD : Format<53>; def MRM_DE : Format<54>; def MRM_DF : Format<55>;
def MRM_E2 : Format<56>; def MRM_E3 : Format<57>; def MRM_E4 : Format<58>; def MRM_E0 : Format<56>; def MRM_E1 : Format<57>; def MRM_E2 : Format<58>;
def MRM_E5 : Format<59>; def MRM_E8 : Format<60>; def MRM_E9 : Format<61>; def MRM_E3 : Format<59>; def MRM_E4 : Format<60>; def MRM_E5 : Format<61>;
def MRM_EA : Format<62>; def MRM_EB : Format<63>; def MRM_EC : Format<64>; def MRM_E8 : Format<62>; def MRM_E9 : Format<63>; def MRM_EA : Format<64>;
def MRM_ED : Format<65>; def MRM_EE : Format<66>; def MRM_F0 : Format<67>; def MRM_EB : Format<65>; def MRM_EC : Format<66>; def MRM_ED : Format<67>;
def MRM_F1 : Format<68>; def MRM_F2 : Format<69>; def MRM_F3 : Format<70>; def MRM_EE : Format<68>; def MRM_F0 : Format<69>; def MRM_F1 : Format<70>;
def MRM_F4 : Format<71>; def MRM_F5 : Format<72>; def MRM_F6 : Format<73>; def MRM_F2 : Format<71>; def MRM_F3 : Format<72>; def MRM_F4 : Format<73>;
def MRM_F7 : Format<74>; def MRM_F8 : Format<75>; def MRM_F9 : Format<76>; def MRM_F5 : Format<74>; def MRM_F6 : Format<75>; def MRM_F7 : Format<76>;
def MRM_FA : Format<77>; def MRM_FB : Format<78>; def MRM_FC : Format<79>; def MRM_F8 : Format<77>; def MRM_F9 : Format<78>; def MRM_FA : Format<79>;
def MRM_FD : Format<80>; def MRM_FE : Format<81>; def MRM_FF : Format<82>; def MRM_FB : Format<80>; def MRM_FC : Format<81>; def MRM_FD : Format<82>;
def MRM_FE : Format<83>; def MRM_FF : Format<84>;
// ImmType - This specifies the immediate type used by an instruction. This is // ImmType - This specifies the immediate type used by an instruction. This is
// part of the ad-hoc solution used to emit machine instruction encodings by our // part of the ad-hoc solution used to emit machine instruction encodings by our

2
lib/Target/X86/X86InstrInfo.td
View File

@@ -748,6 +748,7 @@ def HasHLE : Predicate<"Subtarget->hasHLE()">;
def HasTSX : Predicate<"Subtarget->hasRTM() || Subtarget->hasHLE()">; def HasTSX : Predicate<"Subtarget->hasRTM() || Subtarget->hasHLE()">;
def HasADX : Predicate<"Subtarget->hasADX()">; def HasADX : Predicate<"Subtarget->hasADX()">;
def HasSHA : Predicate<"Subtarget->hasSHA()">; def HasSHA : Predicate<"Subtarget->hasSHA()">;
def HasSGX : Predicate<"Subtarget->hasSGX()">;
def HasPRFCHW : Predicate<"Subtarget->hasPRFCHW()">; def HasPRFCHW : Predicate<"Subtarget->hasPRFCHW()">;
def HasRDSEED : Predicate<"Subtarget->hasRDSEED()">; def HasRDSEED : Predicate<"Subtarget->hasRDSEED()">;
def HasPrefetchW : Predicate<"Subtarget->hasPRFCHW()">; def HasPrefetchW : Predicate<"Subtarget->hasPRFCHW()">;
@@ -2400,6 +2401,7 @@ include "X86InstrVMX.td"
include "X86InstrSVM.td" include "X86InstrSVM.td"
include "X86InstrTSX.td" include "X86InstrTSX.td"
include "X86InstrSGX.td"
// System instructions. // System instructions.
include "X86InstrSystem.td" include "X86InstrSystem.td"

24
lib/Target/X86/X86InstrSGX.td Normal file
View File

@@ -0,0 +1,24 @@
//===-- X86InstrSGX.td - SGX Instruction Set Extension -----*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file describes the instructions that make up the Intel SGX instruction
// set.
//
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
// SGX instructions
// ENCLS - Execute an Enclave System Function of Specified Leaf Number
def ENCLS : I<0x01, MRM_CF, (outs), (ins),
"encls", []>, TB, Requires<[HasSGX]>;
// ENCLU - Execute an Enclave User Function of Specified Leaf Number
def ENCLU : I<0x01, MRM_D7, (outs), (ins),
"enclu", []>, TB, Requires<[HasSGX]>;

1
lib/Target/X86/X86Subtarget.cpp
View File

@@ -277,6 +277,7 @@ void X86Subtarget::initializeEnvironment() {
HasVLX = false; HasVLX = false;
HasADX = false; HasADX = false;
HasSHA = false; HasSHA = false;
HasSGX = false;
HasPRFCHW = false; HasPRFCHW = false;
HasRDSEED = false; HasRDSEED = false;
IsBTMemSlow = false; IsBTMemSlow = false;

4
lib/Target/X86/X86Subtarget.h
View File

@@ -139,6 +139,9 @@ protected:
/// HasSHA - Processor has SHA instructions. /// HasSHA - Processor has SHA instructions.
bool HasSHA; bool HasSHA;
/// HasSGX - Processor has SGX instructions.
bool HasSGX;
/// HasPRFCHW - Processor has PRFCHW instructions. /// HasPRFCHW - Processor has PRFCHW instructions.
bool HasPRFCHW; bool HasPRFCHW;
@@ -341,6 +344,7 @@ public:
bool hasHLE() const { return HasHLE; } bool hasHLE() const { return HasHLE; }
bool hasADX() const { return HasADX; } bool hasADX() const { return HasADX; }
bool hasSHA() const { return HasSHA; } bool hasSHA() const { return HasSHA; }
bool hasSGX() const { return HasSGX; }
bool hasPRFCHW() const { return HasPRFCHW; } bool hasPRFCHW() const { return HasPRFCHW; }
bool hasRDSEED() const { return HasRDSEED; } bool hasRDSEED() const { return HasRDSEED; }
bool isBTMemSlow() const { return IsBTMemSlow; } bool isBTMemSlow() const { return IsBTMemSlow; }

9
test/MC/X86/sgx-encoding.s Normal file
View File

@@ -0,0 +1,9 @@
// RUN: llvm-mc -triple x86_64-unknown-unknown --show-encoding %s | FileCheck %s
// CHECK: encls
// CHECK: encoding: [0x0f,0x01,0xcf]
encls
// CHECK: enclu
// CHECK: encoding: [0x0f,0x01,0xd7]
enclu

115
utils/TableGen/X86RecognizableInstr.cpp
View File

@@ -32,48 +32,50 @@ using namespace llvm;
MAP(C9, 38) \ MAP(C9, 38) \
MAP(CA, 39) \ MAP(CA, 39) \
MAP(CB, 40) \ MAP(CB, 40) \
MAP(D0, 41) \ MAP(CF, 41) \
MAP(D1, 42) \ MAP(D0, 42) \
MAP(D4, 43) \ MAP(D1, 43) \
MAP(D5, 44) \ MAP(D4, 44) \
MAP(D6, 45) \ MAP(D5, 45) \
MAP(D8, 46) \ MAP(D6, 46) \
MAP(D9, 47) \ MAP(D7, 47) \
MAP(DA, 48) \ MAP(D8, 48) \
MAP(DB, 49) \ MAP(D9, 49) \
MAP(DC, 50) \ MAP(DA, 50) \
MAP(DD, 51) \ MAP(DB, 51) \
MAP(DE, 52) \ MAP(DC, 52) \
MAP(DF, 53) \ MAP(DD, 53) \
MAP(E0, 54) \ MAP(DE, 54) \
MAP(E1, 55) \ MAP(DF, 55) \
MAP(E2, 56) \ MAP(E0, 56) \
MAP(E3, 57) \ MAP(E1, 57) \
MAP(E4, 58) \ MAP(E2, 58) \
MAP(E5, 59) \ MAP(E3, 59) \
MAP(E8, 60) \ MAP(E4, 60) \
MAP(E9, 61) \ MAP(E5, 61) \
MAP(EA, 62) \ MAP(E8, 62) \
MAP(EB, 63) \ MAP(E9, 63) \
MAP(EC, 64) \ MAP(EA, 64) \
MAP(ED, 65) \ MAP(EB, 65) \
MAP(EE, 66) \ MAP(EC, 66) \
MAP(F0, 67) \ MAP(ED, 67) \
MAP(F1, 68) \ MAP(EE, 68) \
MAP(F2, 69) \ MAP(F0, 69) \
MAP(F3, 70) \ MAP(F1, 70) \
MAP(F4, 71) \ MAP(F2, 71) \
MAP(F5, 72) \ MAP(F3, 72) \
MAP(F6, 73) \ MAP(F4, 73) \
MAP(F7, 74) \ MAP(F5, 74) \
MAP(F8, 75) \ MAP(F6, 75) \
MAP(F9, 76) \ MAP(F7, 76) \
MAP(FA, 77) \ MAP(F8, 77) \
MAP(FB, 78) \ MAP(F9, 78) \
MAP(FC, 79) \ MAP(FA, 79) \
MAP(FD, 80) \ MAP(FB, 80) \
MAP(FE, 81) \ MAP(FC, 81) \
MAP(FF, 82) MAP(FD, 82) \
MAP(FE, 83) \
MAP(FF, 84)
// A clone of X86 since we can't depend on something that is generated. // A clone of X86 since we can't depend on something that is generated.
namespace X86Local { namespace X86Local {
@@ -769,20 +771,21 @@ void RecognizableInstr::emitInstructionSpecifier() {
case X86Local::MRM_C0: case X86Local::MRM_C1: case X86Local::MRM_C2: case X86Local::MRM_C0: case X86Local::MRM_C1: case X86Local::MRM_C2:
case X86Local::MRM_C3: case X86Local::MRM_C4: case X86Local::MRM_C8: case X86Local::MRM_C3: case X86Local::MRM_C4: case X86Local::MRM_C8:
case X86Local::MRM_C9: case X86Local::MRM_CA: case X86Local::MRM_CB: case X86Local::MRM_C9: case X86Local::MRM_CA: case X86Local::MRM_CB:
case X86Local::MRM_D0: case X86Local::MRM_D1: case X86Local::MRM_D4: case X86Local::MRM_CF: case X86Local::MRM_D0: case X86Local::MRM_D1:
case X86Local::MRM_D5: case X86Local::MRM_D6: case X86Local::MRM_D8: case X86Local::MRM_D4: case X86Local::MRM_D5: case X86Local::MRM_D6:
case X86Local::MRM_D9: case X86Local::MRM_DA: case X86Local::MRM_DB: case X86Local::MRM_D7: case X86Local::MRM_D8: case X86Local::MRM_D9:
case X86Local::MRM_DC: case X86Local::MRM_DD: case X86Local::MRM_DE: case X86Local::MRM_DA: case X86Local::MRM_DB: case X86Local::MRM_DC:
case X86Local::MRM_DF: case X86Local::MRM_E0: case X86Local::MRM_E1: case X86Local::MRM_DD: case X86Local::MRM_DE: case X86Local::MRM_DF:
case X86Local::MRM_E2: case X86Local::MRM_E3: case X86Local::MRM_E4: case X86Local::MRM_E0: case X86Local::MRM_E1: case X86Local::MRM_E2:
case X86Local::MRM_E5: case X86Local::MRM_E8: case X86Local::MRM_E9: case X86Local::MRM_E3: case X86Local::MRM_E4: case X86Local::MRM_E5:
case X86Local::MRM_EA: case X86Local::MRM_EB: case X86Local::MRM_EC: case X86Local::MRM_E8: case X86Local::MRM_E9: case X86Local::MRM_EA:
case X86Local::MRM_ED: case X86Local::MRM_EE: case X86Local::MRM_F0: case X86Local::MRM_EB: case X86Local::MRM_EC: case X86Local::MRM_ED:
case X86Local::MRM_F1: case X86Local::MRM_F2: case X86Local::MRM_F3: case X86Local::MRM_EE: case X86Local::MRM_F0: case X86Local::MRM_F1:
case X86Local::MRM_F4: case X86Local::MRM_F5: case X86Local::MRM_F6: case X86Local::MRM_F2: case X86Local::MRM_F3: case X86Local::MRM_F4:
case X86Local::MRM_F7: case X86Local::MRM_F9: case X86Local::MRM_FA: case X86Local::MRM_F5: case X86Local::MRM_F6: case X86Local::MRM_F7:
case X86Local::MRM_FB: case X86Local::MRM_FC: case X86Local::MRM_FD: case X86Local::MRM_F9: case X86Local::MRM_FA: case X86Local::MRM_FB:
case X86Local::MRM_FE: case X86Local::MRM_FF: case X86Local::MRM_FC: case X86Local::MRM_FD: case X86Local::MRM_FE:
case X86Local::MRM_FF:
// Ignored. // Ignored.
break; break;
} }