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Add simple reg-reg add.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70712 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Anton Korobeynikov 2009-05-03 13:02:39 +00:00
parent fff5f76c46
commit 431beb5fa7
1 changed files with 14 additions and 0 deletions
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14
lib/Target/MSP430/MSP430InstrInfo.td
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@ -60,3 +60,17 @@ def MOV16ri : Pseudo<(outs GR16:$dst), (ins i16imm:$src),
"mov.w\t{$src, $dst|$dst, $src}",
[(set GR16:$dst, imm:$src)]>;
}
//===----------------------------------------------------------------------===//
// Arithmetic Instructions
let Defs = [SR] in {
let isCommutable = 1 in { // X = ADD Y, Z == X = ADD Z, Y
// FIXME: Provide proper encoding!
def ADD16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
"add.w\t{$src2, $dst|$dst, $src2}",
[(set GR16:$dst, (add GR16:$src1, GR16:$src2)),
(implicit SR)]>;
}
}