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[AArch64] Add experimental PBQP support

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This adds target specific support for using the PBQP register allocator on the
AArch64, for the A57 cpu.

By default, the PBQP allocator is not used, unless explicitely required
on the command line with "-aarch64-pbqp".

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217504 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Arnaud A. de Grandmaison
2014-09-10 14:06:10 +00:00
parent 3babc141b2
commit 438669ca81
6 changed files with 449 additions and 2 deletions
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16
lib/Target/AArch64/AArch64TargetMachine.cpp
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@@ -13,6 +13,7 @@
#include "AArch64.h"
#include "AArch64TargetMachine.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/RegAllocRegistry.h"
#include "llvm/PassManager.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/TargetRegistry.h"
@@ -73,6 +74,10 @@ EnableCondOpt("aarch64-condopt",
cl::desc("Enable the condition optimizer pass"),
cl::init(true), cl::Hidden);
static cl::opt<bool>
EnablePBQP("aarch64-pbqp", cl::Hidden,
cl::desc("Use PBQP register allocator (experimental)"),
cl::init(false));
extern "C" void LLVMInitializeAArch64Target() {
// Register the target.
@@ -90,8 +95,14 @@ AArch64TargetMachine::AArch64TargetMachine(const Target &T, StringRef TT,
CodeGenOpt::Level OL,
bool LittleEndian)
: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
Subtarget(TT, CPU, FS, *this, LittleEndian) {
Subtarget(TT, CPU, FS, *this, LittleEndian),
usingPBQP(false) {
initAsmInfo();
if (EnablePBQP && Subtarget.isCortexA57() && OL != CodeGenOpt::None) {
usingPBQP = true;
RegisterRegAlloc::setDefault(createAArch64A57PBQPRegAlloc);
}
}
void AArch64leTargetMachine::anchor() { }
@@ -216,7 +227,8 @@ bool AArch64PassConfig::addPostRegAlloc() {
if (TM->getOptLevel() != CodeGenOpt::None && EnableDeadRegisterElimination)
addPass(createAArch64DeadRegisterDefinitions());
if (TM->getOptLevel() != CodeGenOpt::None &&
TM->getSubtarget<AArch64Subtarget>().isCortexA57())
TM->getSubtarget<AArch64Subtarget>().isCortexA57() &&
!static_cast<const AArch64TargetMachine *>(TM)->isPBQPUsed())
// Improve performance for some FP/SIMD code for A57.
addPass(createAArch64A57FPLoadBalancing());
return true;