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Mass rename for Jim.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114812 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -113,16 +113,16 @@ class ARMFastISel : public FastISel {
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// Instruction selection routines.
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private:
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virtual bool ARMSelectLoad(const Instruction *I);
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virtual bool ARMSelectStore(const Instruction *I);
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virtual bool ARMSelectBranch(const Instruction *I);
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virtual bool ARMSelectCmp(const Instruction *I);
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virtual bool ARMSelectFPExt(const Instruction *I);
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virtual bool ARMSelectFPTrunc(const Instruction *I);
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virtual bool ARMSelectBinaryOp(const Instruction *I, unsigned ISDOpcode);
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virtual bool ARMSelectSIToFP(const Instruction *I);
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virtual bool ARMSelectFPToSI(const Instruction *I);
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virtual bool ARMSelectSDiv(const Instruction *I);
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virtual bool SelectLoad(const Instruction *I);
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virtual bool SelectStore(const Instruction *I);
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virtual bool SelectBranch(const Instruction *I);
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virtual bool SelectCmp(const Instruction *I);
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virtual bool SelectFPExt(const Instruction *I);
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virtual bool SelectFPTrunc(const Instruction *I);
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virtual bool SelectBinaryOp(const Instruction *I, unsigned ISDOpcode);
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virtual bool SelectSIToFP(const Instruction *I);
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virtual bool SelectFPToSI(const Instruction *I);
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virtual bool SelectSDiv(const Instruction *I);
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// Utility routines.
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private:
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@ -602,7 +602,7 @@ bool ARMFastISel::ARMEmitLoad(EVT VT, unsigned &ResultReg,
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return true;
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}
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bool ARMFastISel::ARMSelectLoad(const Instruction *I) {
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bool ARMFastISel::SelectLoad(const Instruction *I) {
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// Verify we have a legal type before going any further.
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EVT VT;
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if (!isLoadTypeLegal(I->getType(), VT))
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@ -689,7 +689,7 @@ bool ARMFastISel::ARMEmitStore(EVT VT, unsigned SrcReg,
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return true;
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}
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bool ARMFastISel::ARMSelectStore(const Instruction *I) {
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bool ARMFastISel::SelectStore(const Instruction *I) {
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Value *Op0 = I->getOperand(0);
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unsigned SrcReg = 0;
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@ -768,14 +768,14 @@ static ARMCC::CondCodes getComparePred(CmpInst::Predicate Pred) {
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}
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}
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bool ARMFastISel::ARMSelectBranch(const Instruction *I) {
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bool ARMFastISel::SelectBranch(const Instruction *I) {
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const BranchInst *BI = cast<BranchInst>(I);
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MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
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MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
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// Simple branch support.
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// TODO: Hopefully we've already handled the condition since we won't
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// have left an update in the value map. See the TODO below in ARMSelectCMP.
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// have left an update in the value map. See the TODO below in SelectCMP.
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Value *Cond = BI->getCondition();
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unsigned CondReg = getRegForValue(Cond);
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if (CondReg == 0) return false;
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@ -798,7 +798,7 @@ bool ARMFastISel::ARMSelectBranch(const Instruction *I) {
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return true;
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}
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bool ARMFastISel::ARMSelectCmp(const Instruction *I) {
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bool ARMFastISel::SelectCmp(const Instruction *I) {
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const CmpInst *CI = cast<CmpInst>(I);
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EVT VT;
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@ -849,7 +849,7 @@ bool ARMFastISel::ARMSelectCmp(const Instruction *I) {
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return true;
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}
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bool ARMFastISel::ARMSelectFPExt(const Instruction *I) {
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bool ARMFastISel::SelectFPExt(const Instruction *I) {
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// Make sure we have VFP and that we're extending float to double.
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if (!Subtarget->hasVFP2()) return false;
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@ -868,7 +868,7 @@ bool ARMFastISel::ARMSelectFPExt(const Instruction *I) {
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return true;
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}
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bool ARMFastISel::ARMSelectFPTrunc(const Instruction *I) {
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bool ARMFastISel::SelectFPTrunc(const Instruction *I) {
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// Make sure we have VFP and that we're truncating double to float.
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if (!Subtarget->hasVFP2()) return false;
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@ -887,7 +887,7 @@ bool ARMFastISel::ARMSelectFPTrunc(const Instruction *I) {
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return true;
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}
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bool ARMFastISel::ARMSelectSIToFP(const Instruction *I) {
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bool ARMFastISel::SelectSIToFP(const Instruction *I) {
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// Make sure we have VFP.
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if (!Subtarget->hasVFP2()) return false;
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@ -917,7 +917,7 @@ bool ARMFastISel::ARMSelectSIToFP(const Instruction *I) {
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return true;
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}
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bool ARMFastISel::ARMSelectFPToSI(const Instruction *I) {
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bool ARMFastISel::SelectFPToSI(const Instruction *I) {
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// Make sure we have VFP.
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if (!Subtarget->hasVFP2()) return false;
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@ -950,7 +950,7 @@ bool ARMFastISel::ARMSelectFPToSI(const Instruction *I) {
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return true;
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}
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bool ARMFastISel::ARMSelectBinaryOp(const Instruction *I, unsigned ISDOpcode) {
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bool ARMFastISel::SelectBinaryOp(const Instruction *I, unsigned ISDOpcode) {
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EVT VT = TLI.getValueType(I->getType(), true);
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// We can get here in the case when we want to use NEON for our fp
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@ -1139,7 +1139,7 @@ bool ARMFastISel::ARMEmitLibcall(const Instruction *I, Function *F) {
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return true;
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}
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bool ARMFastISel::ARMSelectSDiv(const Instruction *I) {
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bool ARMFastISel::SelectSDiv(const Instruction *I) {
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EVT VT;
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const Type *Ty = I->getType();
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if (!isTypeLegal(Ty, VT))
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@ -1180,30 +1180,30 @@ bool ARMFastISel::TargetSelectInstruction(const Instruction *I) {
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switch (I->getOpcode()) {
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case Instruction::Load:
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return ARMSelectLoad(I);
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return SelectLoad(I);
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case Instruction::Store:
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return ARMSelectStore(I);
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return SelectStore(I);
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case Instruction::Br:
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return ARMSelectBranch(I);
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return SelectBranch(I);
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case Instruction::ICmp:
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case Instruction::FCmp:
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return ARMSelectCmp(I);
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return SelectCmp(I);
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case Instruction::FPExt:
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return ARMSelectFPExt(I);
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return SelectFPExt(I);
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case Instruction::FPTrunc:
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return ARMSelectFPTrunc(I);
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return SelectFPTrunc(I);
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case Instruction::SIToFP:
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return ARMSelectSIToFP(I);
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return SelectSIToFP(I);
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case Instruction::FPToSI:
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return ARMSelectFPToSI(I);
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return SelectFPToSI(I);
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case Instruction::FAdd:
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return ARMSelectBinaryOp(I, ISD::FADD);
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return SelectBinaryOp(I, ISD::FADD);
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case Instruction::FSub:
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return ARMSelectBinaryOp(I, ISD::FSUB);
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return SelectBinaryOp(I, ISD::FSUB);
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case Instruction::FMul:
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return ARMSelectBinaryOp(I, ISD::FMUL);
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return SelectBinaryOp(I, ISD::FMUL);
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case Instruction::SDiv:
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return ARMSelectSDiv(I);
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return SelectSDiv(I);
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default: break;
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}
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return false;
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