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another solution to the fsel issue. Instead of having 4 variants, just force

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the comparison to be 64-bits.  This is fine because extensions from float
to double are free.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23589 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2005-10-02 07:07:49 +00:00
parent 867940d1b7
commit 43f07a4bbc
3 changed files with 25 additions and 32 deletions
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20
lib/Target/PowerPC/PPCISelDAGToDAG.cpp
View File

@ -753,18 +753,14 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
return SDOperand(Result.Val, Op.ResNo);
}
case PPCISD::FSEL: {
unsigned Opc;
if (N->getValueType(0) == MVT::f32) {
Opc = N->getOperand(0).getValueType() == MVT::f32 ?
PPC::FSELSS : PPC::FSELSD;
} else {
Opc = N->getOperand(0).getValueType() == MVT::f64 ?
PPC::FSELDD : PPC::FSELDS;
}
CurDAG->SelectNodeTo(N, Opc, N->getValueType(0),
Select(N->getOperand(0)),
Select(N->getOperand(1)),
Select(N->getOperand(2)));
SDOperand Comparison = Select(N->getOperand(0));
// Extend the comparison to 64-bits.
if (Comparison.getValueType() == MVT::f32)
Comparison = CurDAG->getTargetNode(PPC::FMRSD, MVT::f64, Comparison);
unsigned Opc = N->getValueType(0) == MVT::f32 ? PPC::FSELS : PPC::FSELD;
CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), Comparison,
Select(N->getOperand(1)), Select(N->getOperand(2)));
return SDOperand(N, 0);
}
case PPCISD::FCFID:

15
lib/Target/PowerPC/PPCISelPattern.cpp
View File

@ -815,12 +815,15 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
Tmp1 = SelectExpr(N.getOperand(0));
Tmp2 = SelectExpr(N.getOperand(1));
Tmp3 = SelectExpr(N.getOperand(2));
if (N.getOperand(0).getValueType() == MVT::f32)
Opc = N.getOperand(0).getValueType() == MVT::f32 ?
PPC::FSELSS : PPC::FSELSD;
else
Opc = N.getOperand(0).getValueType() == MVT::f64 ?
PPC::FSELDD : PPC::FSELDS;
// Extend the comparison to 64-bits if needed.
if (N.getOperand(0).getValueType() == MVT::f32) {
unsigned Tmp1New = MakeReg(MVT::f64);
BuildMI(BB, PPC::FMRSD, 1, Tmp1New).addReg(Tmp1);
Tmp1 = Tmp1New;
}
Opc = N.Val->getValueType(0) == MVT::f32 ? PPC::FSELS : PPC::FSELD;
BuildMI(BB, Opc, 3, Result).addReg(Tmp1).addReg(Tmp2).addReg(Tmp3);
return Result;
case PPCISD::FCFID:

22
lib/Target/PowerPC/PPCInstrInfo.td
View File

@ -791,21 +791,15 @@ def FNMSUBS : AForm_1<59, 30,
(ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
"fnmsubs $FRT, $FRA, $FRC, $FRB",
[]>;
// FSEL is artificially split into 4 and 8-byte forms for the comparison type
// FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
// having 4 of these, force the comparison to always be an 8-byte double (code
// should use an FMRSD if the input comparison value really wants to be a float)
// and 4/8 byte forms for the result and operand type..
def FSELDD : AForm_1<63, 23,
(ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
"fsel $FRT, $FRA, $FRC, $FRB",
[]>;
def FSELSS : AForm_1<63, 23,
(ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
"fsel $FRT, $FRA, $FRC, $FRB",
[]>;
def FSELDS : AForm_1<63, 23, // result Double, comparison Single
(ops F8RC:$FRT, F4RC:$FRA, F8RC:$FRC, F8RC:$FRB),
"fsel $FRT, $FRA, $FRC, $FRB",
[]>;
def FSELSD : AForm_1<63, 23, // result Single, comparison Double
def FSELD : AForm_1<63, 23,
(ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
"fsel $FRT, $FRA, $FRC, $FRB",
[]>;
def FSELS : AForm_1<63, 23,
(ops F4RC:$FRT, F8RC:$FRA, F4RC:$FRC, F4RC:$FRB),
"fsel $FRT, $FRA, $FRC, $FRB",
[]>;