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Change the post-RA scheduler to iterate through the

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basic-block segments bottom-up instead of top down. This
is the first step in a general restructuring of the way
register liveness is tracked in the post-RA scheduler.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63643 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman 2009-02-03 18:57:45 +00:00
parent 605679f0cd
commit 43f07fb6c3
1 changed files with 11 additions and 9 deletions
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20
lib/CodeGen/PostRASchedulerList.cpp
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@ -189,15 +189,17 @@ bool PostRAScheduler::runOnMachineFunction(MachineFunction &Fn) {
MBB != MBBe; ++MBB) {
// Schedule each sequence of instructions not interrupted by a label
// or anything else that effectively needs to shut down scheduling.
MachineBasicBlock::iterator Current = MBB->begin(), End = MBB->end();
for (MachineBasicBlock::iterator MI = Current; MI != End; ++MI)
MachineBasicBlock::iterator Current = MBB->end(), Top = MBB->begin();
for (MachineBasicBlock::iterator I = Current; I != Top; ) {
MachineInstr *MI = --I;
if (MI->getDesc().isTerminator() || MI->isLabel()) {
Scheduler.Run(0, MBB, Current, MI);
Scheduler.Run(0, MBB, next(I), Current);
Scheduler.EmitSchedule();
Current = next(MI);
Current = I;
}
}
Scheduler.Run(0, MBB, Current, End);
Scheduler.Run(0, MBB, Top, Current);
Scheduler.EmitSchedule();
}
@ -415,10 +417,10 @@ bool SchedulePostRATDList::BreakAntiDependencies() {
// instructions from the bottom up, tracking information about liveness
// as we go to help determine which registers are available.
bool Changed = false;
unsigned Count = BB->size() - 1;
for (MachineBasicBlock::reverse_iterator I = BB->rbegin(), E = BB->rend();
I != E; ++I, --Count) {
MachineInstr *MI = &*I;
unsigned Count = SUnits.size() - 1;
for (MachineBasicBlock::iterator I = End, E = Begin;
I != E; --Count) {
MachineInstr *MI = --I;
// After regalloc, IMPLICIT_DEF instructions aren't safe to treat as
// dependence-breaking. In the case of an INSERT_SUBREG, the IMPLICIT_DEF