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Change the post-RA scheduler to iterate through the
basic-block segments bottom-up instead of top down. This is the first step in a general restructuring of the way register liveness is tracked in the post-RA scheduler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63643 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -189,15 +189,17 @@ bool PostRAScheduler::runOnMachineFunction(MachineFunction &Fn) {
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MBB != MBBe; ++MBB) {
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MBB != MBBe; ++MBB) {
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// Schedule each sequence of instructions not interrupted by a label
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// Schedule each sequence of instructions not interrupted by a label
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// or anything else that effectively needs to shut down scheduling.
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// or anything else that effectively needs to shut down scheduling.
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MachineBasicBlock::iterator Current = MBB->begin(), End = MBB->end();
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MachineBasicBlock::iterator Current = MBB->end(), Top = MBB->begin();
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for (MachineBasicBlock::iterator MI = Current; MI != End; ++MI)
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for (MachineBasicBlock::iterator I = Current; I != Top; ) {
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MachineInstr *MI = --I;
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if (MI->getDesc().isTerminator() || MI->isLabel()) {
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if (MI->getDesc().isTerminator() || MI->isLabel()) {
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Scheduler.Run(0, MBB, Current, MI);
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Scheduler.Run(0, MBB, next(I), Current);
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Scheduler.EmitSchedule();
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Scheduler.EmitSchedule();
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Current = next(MI);
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Current = I;
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}
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}
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}
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Scheduler.Run(0, MBB, Current, End);
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Scheduler.Run(0, MBB, Top, Current);
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Scheduler.EmitSchedule();
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Scheduler.EmitSchedule();
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}
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}
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@ -415,10 +417,10 @@ bool SchedulePostRATDList::BreakAntiDependencies() {
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// instructions from the bottom up, tracking information about liveness
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// instructions from the bottom up, tracking information about liveness
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// as we go to help determine which registers are available.
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// as we go to help determine which registers are available.
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bool Changed = false;
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bool Changed = false;
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unsigned Count = BB->size() - 1;
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unsigned Count = SUnits.size() - 1;
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for (MachineBasicBlock::reverse_iterator I = BB->rbegin(), E = BB->rend();
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for (MachineBasicBlock::iterator I = End, E = Begin;
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I != E; ++I, --Count) {
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I != E; --Count) {
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MachineInstr *MI = &*I;
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MachineInstr *MI = --I;
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// After regalloc, IMPLICIT_DEF instructions aren't safe to treat as
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// After regalloc, IMPLICIT_DEF instructions aren't safe to treat as
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// dependence-breaking. In the case of an INSERT_SUBREG, the IMPLICIT_DEF
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// dependence-breaking. In the case of an INSERT_SUBREG, the IMPLICIT_DEF
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