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improve x86 codegen support for blockaddress. We now compile
the testcase into: _test1: ## @test1 ## BB#0: ## %entry leaq L_test1_bb6(%rip), %rax jmpq *%rax L_test1_bb: ## Address Taken LBB1_1: ## %bb movb $1, %al ret L_test1_bb6: ## Address Taken LBB1_2: ## %bb6 movb $2, %al ret Note, it is very very strange that BlockAddressSDNode doesn't carry around TargetFlags. Dan, please fix this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85703 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -71,6 +71,7 @@ namespace {
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SDValue Segment;
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SDValue Segment;
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GlobalValue *GV;
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GlobalValue *GV;
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Constant *CP;
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Constant *CP;
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BlockAddress *BlockAddr;
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const char *ES;
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const char *ES;
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int JT;
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int JT;
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unsigned Align; // CP alignment.
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unsigned Align; // CP alignment.
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@ -78,12 +79,12 @@ namespace {
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X86ISelAddressMode()
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X86ISelAddressMode()
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: BaseType(RegBase), Scale(1), IndexReg(), Disp(0),
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: BaseType(RegBase), Scale(1), IndexReg(), Disp(0),
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Segment(), GV(0), CP(0), ES(0), JT(-1), Align(0),
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Segment(), GV(0), CP(0), BlockAddr(0), ES(0), JT(-1), Align(0),
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SymbolFlags(X86II::MO_NO_FLAG) {
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SymbolFlags(X86II::MO_NO_FLAG) {
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}
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}
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bool hasSymbolicDisplacement() const {
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bool hasSymbolicDisplacement() const {
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return GV != 0 || CP != 0 || ES != 0 || JT != -1;
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return GV != 0 || CP != 0 || ES != 0 || JT != -1 || BlockAddr != 0;
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}
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}
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bool hasBaseOrIndexReg() const {
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bool hasBaseOrIndexReg() const {
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@ -241,6 +242,9 @@ namespace {
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Disp = CurDAG->getTargetExternalSymbol(AM.ES, MVT::i32, AM.SymbolFlags);
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Disp = CurDAG->getTargetExternalSymbol(AM.ES, MVT::i32, AM.SymbolFlags);
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else if (AM.JT != -1)
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else if (AM.JT != -1)
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Disp = CurDAG->getTargetJumpTable(AM.JT, MVT::i32, AM.SymbolFlags);
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Disp = CurDAG->getTargetJumpTable(AM.JT, MVT::i32, AM.SymbolFlags);
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else if (AM.BlockAddr)
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Disp = CurDAG->getBlockAddress(AM.BlockAddr, DebugLoc()/*MVT::i32*/,
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true /*AM.SymbolFlags*/);
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else
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else
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Disp = CurDAG->getTargetConstant(AM.Disp, MVT::i32);
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Disp = CurDAG->getTargetConstant(AM.Disp, MVT::i32);
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@ -760,10 +764,12 @@ bool X86DAGToDAGISel::MatchWrapper(SDValue N, X86ISelAddressMode &AM) {
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} else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(N0)) {
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} else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(N0)) {
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AM.ES = S->getSymbol();
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AM.ES = S->getSymbol();
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AM.SymbolFlags = S->getTargetFlags();
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AM.SymbolFlags = S->getTargetFlags();
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} else {
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} else if (JumpTableSDNode *J = dyn_cast<JumpTableSDNode>(N0)) {
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JumpTableSDNode *J = cast<JumpTableSDNode>(N0);
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AM.JT = J->getIndex();
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AM.JT = J->getIndex();
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AM.SymbolFlags = J->getTargetFlags();
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AM.SymbolFlags = J->getTargetFlags();
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} else {
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AM.BlockAddr = cast<BlockAddressSDNode>(N0)->getBlockAddress();
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//AM.SymbolFlags = cast<BlockAddressSDNode>(N0)->getTargetFlags();
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}
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}
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if (N.getOpcode() == X86ISD::WrapperRIP)
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if (N.getOpcode() == X86ISD::WrapperRIP)
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@ -789,10 +795,12 @@ bool X86DAGToDAGISel::MatchWrapper(SDValue N, X86ISelAddressMode &AM) {
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} else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(N0)) {
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} else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(N0)) {
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AM.ES = S->getSymbol();
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AM.ES = S->getSymbol();
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AM.SymbolFlags = S->getTargetFlags();
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AM.SymbolFlags = S->getTargetFlags();
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} else {
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} else if (JumpTableSDNode *J = dyn_cast<JumpTableSDNode>(N0)) {
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JumpTableSDNode *J = cast<JumpTableSDNode>(N0);
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AM.JT = J->getIndex();
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AM.JT = J->getIndex();
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AM.SymbolFlags = J->getTargetFlags();
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AM.SymbolFlags = J->getTargetFlags();
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} else {
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AM.BlockAddr = cast<BlockAddressSDNode>(N0)->getBlockAddress();
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//AM.SymbolFlags = cast<BlockAddressSDNode>(N0)->getTargetFlags();
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}
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}
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return false;
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return false;
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}
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}
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16
test/CodeGen/X86/x86-64-jumps.ll
Normal file
16
test/CodeGen/X86/x86-64-jumps.ll
Normal file
@ -0,0 +1,16 @@
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; RUN: llc < %s
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
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target triple = "x86_64-apple-darwin10.0"
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define i8 @test1() nounwind ssp {
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entry:
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%0 = select i1 undef, i8* blockaddress(@test1, %bb), i8* blockaddress(@test1, %bb6) ; <i8*> [#uses=1]
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indirectbr i8* %0, [label %bb, label %bb6]
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bb: ; preds = %entry
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ret i8 1
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bb6: ; preds = %entry
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ret i8 2
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}
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