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ARM64: shuffle patterns around for fmin/fmax & add tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205205 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -2857,12 +2857,20 @@ def : Pat<(f32 (int_arm64_neon_faddv (v4f32 V128:$Rn))),
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(FADDPv2i32p (EXTRACT_SUBREG (FADDPv4f32 V128:$Rn, V128:$Rn), dsub))>;
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(FADDPv2i32p (EXTRACT_SUBREG (FADDPv4f32 V128:$Rn, V128:$Rn), dsub))>;
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def : Pat<(f64 (int_arm64_neon_faddv (v2f64 V128:$Rn))),
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def : Pat<(f64 (int_arm64_neon_faddv (v2f64 V128:$Rn))),
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(FADDPv2i64p V128:$Rn)>;
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(FADDPv2i64p V128:$Rn)>;
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def : Pat<(f32 (int_arm64_neon_fmaxnmv (v2f32 V64:$Rn))),
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(FMAXNMPv2i32p V64:$Rn)>;
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def : Pat<(f64 (int_arm64_neon_fmaxnmv (v2f64 V128:$Rn))),
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def : Pat<(f64 (int_arm64_neon_fmaxnmv (v2f64 V128:$Rn))),
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(FMAXNMPv2i64p V128:$Rn)>;
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(FMAXNMPv2i64p V128:$Rn)>;
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def : Pat<(f32 (int_arm64_neon_fmaxv (v2f32 V64:$Rn))),
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(FMAXPv2i32p V64:$Rn)>;
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def : Pat<(f64 (int_arm64_neon_fmaxv (v2f64 V128:$Rn))),
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def : Pat<(f64 (int_arm64_neon_fmaxv (v2f64 V128:$Rn))),
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(FMAXPv2i64p V128:$Rn)>;
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(FMAXPv2i64p V128:$Rn)>;
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def : Pat<(f32 (int_arm64_neon_fminnmv (v2f32 V64:$Rn))),
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(FMINNMPv2i32p V64:$Rn)>;
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def : Pat<(f64 (int_arm64_neon_fminnmv (v2f64 V128:$Rn))),
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def : Pat<(f64 (int_arm64_neon_fminnmv (v2f64 V128:$Rn))),
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(FMINNMPv2i64p V128:$Rn)>;
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(FMINNMPv2i64p V128:$Rn)>;
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def : Pat<(f32 (int_arm64_neon_fminv (v2f32 V64:$Rn))),
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(FMINPv2i32p V64:$Rn)>;
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def : Pat<(f64 (int_arm64_neon_fminv (v2f64 V128:$Rn))),
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def : Pat<(f64 (int_arm64_neon_fminv (v2f64 V128:$Rn))),
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(FMINPv2i64p V128:$Rn)>;
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(FMINPv2i64p V128:$Rn)>;
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@ -3072,17 +3080,9 @@ defm UMINV : SIMDAcrossLanesBHS<1, 0b11010, "uminv">;
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defm SADDLV : SIMDAcrossLanesHSD<0, 0b00011, "saddlv">;
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defm SADDLV : SIMDAcrossLanesHSD<0, 0b00011, "saddlv">;
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defm UADDLV : SIMDAcrossLanesHSD<1, 0b00011, "uaddlv">;
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defm UADDLV : SIMDAcrossLanesHSD<1, 0b00011, "uaddlv">;
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defm FMAXNMV : SIMDAcrossLanesS<0b01100, 0, "fmaxnmv", int_arm64_neon_fmaxnmv>;
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defm FMAXNMV : SIMDAcrossLanesS<0b01100, 0, "fmaxnmv", int_arm64_neon_fmaxnmv>;
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def : Pat<(f32 (int_arm64_neon_fmaxnmv (v2f32 V64:$Rn))),
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(EXTRACT_SUBREG (FMAXNMPv2f32 V64:$Rn, V64:$Rn), ssub)>;
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defm FMAXV : SIMDAcrossLanesS<0b01111, 0, "fmaxv", int_arm64_neon_fmaxv>;
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defm FMAXV : SIMDAcrossLanesS<0b01111, 0, "fmaxv", int_arm64_neon_fmaxv>;
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def : Pat<(f32 (int_arm64_neon_fmaxv (v2f32 V64:$Rn))),
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(EXTRACT_SUBREG (FMAXPv2f32 V64:$Rn, V64:$Rn), ssub)>;
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defm FMINNMV : SIMDAcrossLanesS<0b01100, 1, "fminnmv", int_arm64_neon_fminnmv>;
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defm FMINNMV : SIMDAcrossLanesS<0b01100, 1, "fminnmv", int_arm64_neon_fminnmv>;
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def : Pat<(f32 (int_arm64_neon_fminnmv (v2f32 V64:$Rn))),
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(EXTRACT_SUBREG (FMINNMPv2f32 V64:$Rn, V64:$Rn), ssub)>;
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defm FMINV : SIMDAcrossLanesS<0b01111, 1, "fminv", int_arm64_neon_fminv>;
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defm FMINV : SIMDAcrossLanesS<0b01111, 1, "fminv", int_arm64_neon_fminv>;
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def : Pat<(f32 (int_arm64_neon_fminv (v2f32 V64:$Rn))),
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(EXTRACT_SUBREG (FMINPv2f32 V64:$Rn, V64:$Rn), ssub)>;
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multiclass SIMDAcrossLanesSignedIntrinsic<string baseOpc, Intrinsic intOp> {
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multiclass SIMDAcrossLanesSignedIntrinsic<string baseOpc, Intrinsic intOp> {
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// If there is a sign extension after this intrinsic, consume it as smov already
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// If there is a sign extension after this intrinsic, consume it as smov already
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101
test/CodeGen/ARM64/fminv.ll
Normal file
101
test/CodeGen/ARM64/fminv.ll
Normal file
@ -0,0 +1,101 @@
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; RUN: llc -mtriple=arm64-linux-gnu -o - %s | FileCheck %s
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define float @test_fminv_v2f32(<2 x float> %in) {
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; CHECK: test_fminv_v2f32:
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; CHECK: fminp s0, v0.2s
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%min = call float @llvm.arm64.neon.fminv.f32.v2f32(<2 x float> %in)
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ret float %min
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}
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define float @test_fminv_v4f32(<4 x float> %in) {
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; CHECK: test_fminv_v4f32:
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; CHECK: fminv s0, v0.4s
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%min = call float @llvm.arm64.neon.fminv.f32.v4f32(<4 x float> %in)
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ret float %min
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}
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define double @test_fminv_v2f64(<2 x double> %in) {
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; CHECK: test_fminv_v2f64:
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; CHECK: fminp d0, v0.2d
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%min = call double @llvm.arm64.neon.fminv.f64.v2f64(<2 x double> %in)
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ret double %min
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}
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declare float @llvm.arm64.neon.fminv.f32.v2f32(<2 x float>)
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declare float @llvm.arm64.neon.fminv.f32.v4f32(<4 x float>)
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declare double @llvm.arm64.neon.fminv.f64.v2f64(<2 x double>)
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define float @test_fmaxv_v2f32(<2 x float> %in) {
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; CHECK: test_fmaxv_v2f32:
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; CHECK: fmaxp s0, v0.2s
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%max = call float @llvm.arm64.neon.fmaxv.f32.v2f32(<2 x float> %in)
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ret float %max
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}
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define float @test_fmaxv_v4f32(<4 x float> %in) {
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; CHECK: test_fmaxv_v4f32:
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; CHECK: fmaxv s0, v0.4s
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%max = call float @llvm.arm64.neon.fmaxv.f32.v4f32(<4 x float> %in)
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ret float %max
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}
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define double @test_fmaxv_v2f64(<2 x double> %in) {
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; CHECK: test_fmaxv_v2f64:
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; CHECK: fmaxp d0, v0.2d
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%max = call double @llvm.arm64.neon.fmaxv.f64.v2f64(<2 x double> %in)
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ret double %max
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}
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declare float @llvm.arm64.neon.fmaxv.f32.v2f32(<2 x float>)
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declare float @llvm.arm64.neon.fmaxv.f32.v4f32(<4 x float>)
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declare double @llvm.arm64.neon.fmaxv.f64.v2f64(<2 x double>)
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define float @test_fminnmv_v2f32(<2 x float> %in) {
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; CHECK: test_fminnmv_v2f32:
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; CHECK: fminnmp s0, v0.2s
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%minnm = call float @llvm.arm64.neon.fminnmv.f32.v2f32(<2 x float> %in)
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ret float %minnm
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}
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define float @test_fminnmv_v4f32(<4 x float> %in) {
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; CHECK: test_fminnmv_v4f32:
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; CHECK: fminnmv s0, v0.4s
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%minnm = call float @llvm.arm64.neon.fminnmv.f32.v4f32(<4 x float> %in)
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ret float %minnm
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}
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define double @test_fminnmv_v2f64(<2 x double> %in) {
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; CHECK: test_fminnmv_v2f64:
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; CHECK: fminnmp d0, v0.2d
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%minnm = call double @llvm.arm64.neon.fminnmv.f64.v2f64(<2 x double> %in)
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ret double %minnm
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}
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declare float @llvm.arm64.neon.fminnmv.f32.v2f32(<2 x float>)
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declare float @llvm.arm64.neon.fminnmv.f32.v4f32(<4 x float>)
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declare double @llvm.arm64.neon.fminnmv.f64.v2f64(<2 x double>)
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define float @test_fmaxnmv_v2f32(<2 x float> %in) {
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; CHECK: test_fmaxnmv_v2f32:
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; CHECK: fmaxnmp s0, v0.2s
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%maxnm = call float @llvm.arm64.neon.fmaxnmv.f32.v2f32(<2 x float> %in)
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ret float %maxnm
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}
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define float @test_fmaxnmv_v4f32(<4 x float> %in) {
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; CHECK: test_fmaxnmv_v4f32:
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; CHECK: fmaxnmv s0, v0.4s
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%maxnm = call float @llvm.arm64.neon.fmaxnmv.f32.v4f32(<4 x float> %in)
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ret float %maxnm
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}
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define double @test_fmaxnmv_v2f64(<2 x double> %in) {
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; CHECK: test_fmaxnmv_v2f64:
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; CHECK: fmaxnmp d0, v0.2d
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%maxnm = call double @llvm.arm64.neon.fmaxnmv.f64.v2f64(<2 x double> %in)
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ret double %maxnm
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}
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declare float @llvm.arm64.neon.fmaxnmv.f32.v2f32(<2 x float>)
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declare float @llvm.arm64.neon.fmaxnmv.f32.v4f32(<4 x float>)
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declare double @llvm.arm64.neon.fmaxnmv.f64.v2f64(<2 x double>)
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