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refactor things a bit, now the REX_W and OpSize prefix bytes are inferred from the type info.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115745 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -495,11 +495,13 @@ let CodeSize = 2 in {
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} // CodeSize = 2
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} // Defs = [EFLAGS]
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/// X86TypeInfo - This is a bunch of information that describes relevant X86
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/// information about value types. For example, it can tell you what the
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/// register class and preferred load to use.
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class X86TypeInfo<ValueType vt, string instrsuffix, RegisterClass regclass,
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PatFrag loadnode, X86MemOperand memoperand> {
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PatFrag loadnode, X86MemOperand memoperand,
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bit hasOpSizePrefix, bit hasREX_WPrefix> {
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/// VT - This is the value type itself.
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ValueType VT = vt;
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@ -518,33 +520,55 @@ class X86TypeInfo<ValueType vt, string instrsuffix, RegisterClass regclass,
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/// MemOperand - This is the memory operand associated with this type. For
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/// example, i8 -> i8mem, i16 -> i16mem, i32 -> i32mem, i64 -> i64mem.
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X86MemOperand MemOperand = memoperand;
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/// HasOpSizePrefix - This bit is set to true if the instruction should have
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/// the 0x66 operand size prefix. This is set for i16 types.
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bit HasOpSizePrefix = hasOpSizePrefix;
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/// HasREX_WPrefix - This bit is set to true if the instruction should have
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/// the 0x40 REX prefix. This is set for i64 types.
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bit HasREX_WPrefix = hasREX_WPrefix;
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}
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def Xi8 : X86TypeInfo<i8 , "b", GR8 , loadi8 , i8mem>;
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def Xi16 : X86TypeInfo<i16, "w", GR16, loadi16, i16mem>;
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def Xi32 : X86TypeInfo<i32, "l", GR32, loadi32, i32mem>;
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def Xi64 : X86TypeInfo<i64, "q", GR64, loadi64, i64mem>;
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def Xi8 : X86TypeInfo<i8 , "b", GR8 , loadi8 , i8mem , 0, 0>;
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def Xi16 : X86TypeInfo<i16, "w", GR16, loadi16, i16mem, 1, 0>;
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def Xi32 : X86TypeInfo<i32, "l", GR32, loadi32, i32mem, 0, 0>;
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def Xi64 : X86TypeInfo<i64, "q", GR64, loadi64, i64mem, 0, 1>;
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/// ITy - This instruction base class takes the type info for the instruction.
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/// Using this, it:
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/// 1. Concatenates together the instruction mnemonic with the appropriate
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/// suffix letter, a tab, and the arguments.
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/// 2. Infers whether the instruction should have a 0x66 prefix byte.
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/// 3. Infers whether the instruction should have a 0x40 REX_W prefix.
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class ITy<bits<8> opcode, Format f, X86TypeInfo typeinfo, dag outs, dag ins,
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string mnemonic, string args, list<dag> pattern>
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: I<opcode, f, outs, ins,
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!strconcat(mnemonic, "{", typeinfo.InstrSuffix, "}\t", args), pattern> {
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// Infer instruction prefixes from type info.
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let hasOpSizePrefix = typeinfo.HasOpSizePrefix;
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let hasREX_WPrefix = typeinfo.HasREX_WPrefix;
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}
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class BinOpRR<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
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SDNode opnode, Format format>
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: I<opcode, format,
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(outs typeinfo.RegClass:$dst),
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(ins typeinfo.RegClass:$src1, typeinfo.RegClass:$src2),
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!strconcat(mnemonic, "{", typeinfo.InstrSuffix,
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"}\t{$src2, $dst|$dst, $src2}"),
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[(set typeinfo.RegClass:$dst, EFLAGS,
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(opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2))]>;
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: ITy<opcode, format, typeinfo,
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(outs typeinfo.RegClass:$dst),
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(ins typeinfo.RegClass:$src1, typeinfo.RegClass:$src2),
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mnemonic, "{$src2, $dst|$dst, $src2}",
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[(set typeinfo.RegClass:$dst, EFLAGS,
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(opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2))]>;
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class BinOpRM<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
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SDNode opnode>
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: I<opcode, MRMSrcMem,
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(outs typeinfo.RegClass:$dst),
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(ins typeinfo.RegClass:$src1, typeinfo.MemOperand:$src2),
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!strconcat(mnemonic, "{", typeinfo.InstrSuffix,
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"}\t{$src2, $dst|$dst, $src2}"),
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[(set typeinfo.RegClass:$dst, EFLAGS,
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: ITy<opcode, MRMSrcMem, typeinfo,
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(outs typeinfo.RegClass:$dst),
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(ins typeinfo.RegClass:$src1, typeinfo.MemOperand:$src2),
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mnemonic, "{$src2, $dst|$dst, $src2}",
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[(set typeinfo.RegClass:$dst, EFLAGS,
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(opnode typeinfo.RegClass:$src1, (typeinfo.LoadNode addr:$src2)))]>;
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@ -554,9 +578,9 @@ let Constraints = "$src1 = $dst" in {
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let isCommutable = 1 in { // X = AND Y, Z --> X = AND Z, Y
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def AND8rr : BinOpRR<0x20, "and", Xi8 , X86and_flag, MRMDestReg>;
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def AND16rr : BinOpRR<0x21, "and", Xi16, X86and_flag, MRMDestReg>, OpSize;
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def AND16rr : BinOpRR<0x21, "and", Xi16, X86and_flag, MRMDestReg>;
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def AND32rr : BinOpRR<0x21, "and", Xi32, X86and_flag, MRMDestReg>;
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def AND64rr : BinOpRR<0x21, "and", Xi64, X86and_flag, MRMDestReg>, REX_W;
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def AND64rr : BinOpRR<0x21, "and", Xi64, X86and_flag, MRMDestReg>;
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} // isCommutable
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@ -577,9 +601,9 @@ def AND64rr_REV : RI<0x23, MRMSrcReg, (outs GR64:$dst),
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}
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def AND8rm : BinOpRM<0x22, "and", Xi8 , X86and_flag>;
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def AND16rm : BinOpRM<0x23, "and", Xi16, X86and_flag>, OpSize;
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def AND16rm : BinOpRM<0x23, "and", Xi16, X86and_flag>;
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def AND32rm : BinOpRM<0x23, "and", Xi32, X86and_flag>;
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def AND64rm : BinOpRM<0x23, "and", Xi64, X86and_flag>, REX_W;
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def AND64rm : BinOpRM<0x23, "and", Xi64, X86and_flag>;
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def AND8ri : Ii8<0x80, MRM4r,
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(outs GR8 :$dst), (ins GR8 :$src1, i8imm :$src2),
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