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Fix ARM's b.w instruction for thumb 2 and the encoding T4. The branch target
is 24 bits not 20 and the decoding needed to correctly handle converting the J1 and J2 bits to their I1 and I2 values to reconstruct the displacement. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166982 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -3245,11 +3245,11 @@ def t2B : T2I<(outs), (ins uncondbrtarget:$target), IIC_Br,
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let Inst{15-14} = 0b10;
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let Inst{15-14} = 0b10;
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let Inst{12} = 1;
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let Inst{12} = 1;
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bits<20> target;
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bits<24> target;
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let Inst{26} = target{19};
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let Inst{26} = target{19};
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let Inst{11} = target{18};
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let Inst{11} = target{18};
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let Inst{13} = target{17};
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let Inst{13} = target{17};
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let Inst{21-16} = target{16-11};
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let Inst{25-16} = target{20-11};
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let Inst{10-0} = target{10-0};
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let Inst{10-0} = target{10-0};
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let DecoderMethod = "DecodeT2BInstruction";
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let DecoderMethod = "DecodeT2BInstruction";
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}
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}
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@ -2095,16 +2095,28 @@ static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
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static DecodeStatus
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static DecodeStatus
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DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
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DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
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uint64_t Address, const void *Decoder) {
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uint64_t Address, const void *Decoder) {
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DecodeStatus S = MCDisassembler::Success;
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DecodeStatus Status = MCDisassembler::Success;
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unsigned imm = (fieldFromInstruction(Insn, 0, 11) << 0) |
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(fieldFromInstruction(Insn, 11, 1) << 18) |
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// Note the J1 and J2 values are from the encoded instruction. So here
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(fieldFromInstruction(Insn, 13, 1) << 17) |
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// change them to I1 and I2 values via as documented:
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(fieldFromInstruction(Insn, 16, 6) << 11) |
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// I1 = NOT(J1 EOR S);
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(fieldFromInstruction(Insn, 26, 1) << 19);
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// I2 = NOT(J2 EOR S);
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if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<20>(imm<<1) + 4,
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// and build the imm32 with one trailing zero as documented:
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// imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
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unsigned S = fieldFromInstruction(Insn, 26, 1);
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unsigned J1 = fieldFromInstruction(Insn, 13, 1);
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unsigned J2 = fieldFromInstruction(Insn, 11, 1);
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unsigned I1 = !(J1 ^ S);
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unsigned I2 = !(J2 ^ S);
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unsigned imm10 = fieldFromInstruction(Insn, 16, 10);
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unsigned imm11 = fieldFromInstruction(Insn, 0, 11);
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unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11;
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int imm32 = SignExtend32<24>(tmp << 1);
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if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
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true, 4, Inst, Decoder))
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true, 4, Inst, Decoder))
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Inst.addOperand(MCOperand::CreateImm(SignExtend32<20>(imm << 1)));
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Inst.addOperand(MCOperand::CreateImm(imm32));
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return S;
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return Status;
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}
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}
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static DecodeStatus
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static DecodeStatus
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12
test/MC/ARM/thumb2-b.w-encodingT4.s
Normal file
12
test/MC/ARM/thumb2-b.w-encodingT4.s
Normal file
@ -0,0 +1,12 @@
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@ RUN: llvm-mc -triple=thumbv7-apple-darwin -mcpu=cortex-a8 -show-encoding < %s | FileCheck %s
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.syntax unified
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.globl _func
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.thumb_func _foo
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.space 0x37c6
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_foo:
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@------------------------------------------------------------------------------
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@ B (thumb2 b.w encoding T4) rdar://12585795
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@------------------------------------------------------------------------------
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b.w 0x3680c
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@ CHECK: b.w #223244 @ encoding: [0x6d,0xf0,0x0c,0xb0]
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@ -169,6 +169,9 @@
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0x13 0xf5 0xce 0xa9
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0x13 0xf5 0xce 0xa9
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# CHECK: b.w #208962
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0x33 0xf0 0x21 0xb8 # rdar://12585795
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#------------------------------------------------------------------------------
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#------------------------------------------------------------------------------
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# BFC
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# BFC
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