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fp_round's produced by getCopyFromParts should always be exact, because
they are produced by calls (which are known exact) and by cross block copies which are known to be produced by extends. This improves: define double @test2() { %tmp85 = call double asm sideeffect "fld0", "={st(0)}"() ret double %tmp85 } from: _test2: subl $20, %esp # InlineAsm Start fld0 # InlineAsm End fstpl 8(%esp) movsd 8(%esp), %xmm0 movsd %xmm0, (%esp) fldl (%esp) addl $20, %esp #FP_REG_KILL ret to: _test2: # InlineAsm Start fld0 # InlineAsm End #FP_REG_KILL ret by avoiding a f64 <-> f80 trip git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48108 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -628,15 +628,13 @@ public:
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/// combined into the value they represent. If the parts combine to a type
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/// larger then ValueVT then AssertOp can be used to specify whether the extra
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/// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
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/// (ISD::AssertSext). Likewise TruncExact is used for floating point types to
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/// indicate that the extra bits can be discarded without losing precision.
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/// (ISD::AssertSext).
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static SDOperand getCopyFromParts(SelectionDAG &DAG,
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const SDOperand *Parts,
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unsigned NumParts,
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MVT::ValueType PartVT,
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MVT::ValueType ValueVT,
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ISD::NodeType AssertOp = ISD::DELETED_NODE,
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bool TruncExact = false) {
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ISD::NodeType AssertOp = ISD::DELETED_NODE) {
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assert(NumParts > 0 && "No parts to assemble!");
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TargetLowering &TLI = DAG.getTargetLoweringInfo();
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SDOperand Val = Parts[0];
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@ -761,8 +759,9 @@ static SDOperand getCopyFromParts(SelectionDAG &DAG,
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if (MVT::isFloatingPoint(PartVT) && MVT::isFloatingPoint(ValueVT)) {
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if (ValueVT < Val.getValueType())
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// FP_ROUND's are always exact here.
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return DAG.getNode(ISD::FP_ROUND, ValueVT, Val,
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DAG.getIntPtrConstant(TruncExact));
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DAG.getIntPtrConstant(1));
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return DAG.getNode(ISD::FP_EXTEND, ValueVT, Val);
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}
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@ -3267,7 +3266,8 @@ SDOperand RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
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}
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// Assemble the legal parts into the final value.
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return getCopyFromParts(DAG, &Parts[0], NumParts, RegVT, ValueVT);
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return getCopyFromParts(DAG, &Parts[0], NumParts, RegVT, ValueVT,
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ISD::DELETED_NODE);
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}
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/// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
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@ -4147,7 +4147,7 @@ TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
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AssertOp = ISD::AssertZext;
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Ops.push_back(getCopyFromParts(DAG, &Parts[0], NumParts, PartVT, VT,
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AssertOp, true));
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AssertOp));
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}
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assert(i == NumArgRegs && "Argument register count mismatch!");
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return Ops;
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@ -4257,7 +4257,7 @@ TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
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for (unsigned i = 0; i != NumRegs; ++i)
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Results[i] = Res.getValue(i);
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Res = getCopyFromParts(DAG, &Results[0], NumRegs, RegisterVT, VT,
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AssertOp, true);
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AssertOp);
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}
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return std::make_pair(Res, Chain);
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