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https://github.com/c64scene-ar/llvm-6502.git
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Stub out the rest of the DAG Combiner. Just need to fill in the
select_cc bits and then wrap it in a convenience function for use with regular select. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23389 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nate Begeman
parent
cea8688ee4
commit
44728a7bb6
@ -20,6 +20,14 @@
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// ZERO_EXTEND/SIGN_EXTEND by converting them to an ANY_EXTEND node which
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// we don't have yet.
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//
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// FIXME: select C, 16, 0 -> shr C, 4
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// FIXME: select C, pow2, pow2 -> something smart
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// FIXME: trunc(select X, Y, Z) -> select X, trunc(Y), trunc(Z)
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// FIXME: (select C, load A, load B) -> load (select C, A, B)
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// FIXME: store -> load -> forward substitute
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// FIXME: Dead stores -> nuke
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// FIXME: shr X, (and Y,31) -> shr X, Y
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// FIXME: TRUNC (LOAD) -> EXT_LOAD/LOAD(smaller)
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// FIXME: mul (x, const) -> shifts + adds
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// FIXME: undef values
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// FIXME: zero extend when top bits are 0 -> drop it ?
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@ -117,10 +125,13 @@ namespace {
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SDOperand visitFNEG(SDNode *N);
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SDOperand visitFABS(SDNode *N);
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SDOperand visitBRCOND(SDNode *N);
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// brcondtwoway
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// br_cc
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// brtwoway_cc
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SDOperand visitBRCONDTWOWAY(SDNode *N);
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SDOperand visitBR_CC(SDNode *N);
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SDOperand visitBRTWOWAY_CC(SDNode *N);
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SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2);
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SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2,
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SDOperand N3, ISD::CondCode CC);
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SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1,
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ISD::CondCode Cond);
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public:
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@ -339,6 +350,10 @@ SDOperand DAGCombiner::visit(SDNode *N) {
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case ISD::FP_EXTEND: return visitFP_EXTEND(N);
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case ISD::FNEG: return visitFNEG(N);
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case ISD::FABS: return visitFABS(N);
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case ISD::BRCOND: return visitBRCOND(N);
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case ISD::BRCONDTWOWAY: return visitBRCONDTWOWAY(N);
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case ISD::BR_CC: return visitBR_CC(N);
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case ISD::BRTWOWAY_CC: return visitBRTWOWAY_CC(N);
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}
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return SDOperand();
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}
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@ -1029,7 +1044,7 @@ SDOperand DAGCombiner::visitSELECT(SDNode *N) {
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ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
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ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
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MVT::ValueType VT = N->getValueType(0);
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// fold select C, X, X -> X
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if (N1 == N2)
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return N1;
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@ -1040,7 +1055,7 @@ SDOperand DAGCombiner::visitSELECT(SDNode *N) {
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if (N0C && N0C->isNullValue())
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return N2;
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// fold select C, 1, X -> C | X
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if (MVT::i1 == VT && N1C && !N1C->isNullValue())
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if (MVT::i1 == VT && N1C && N1C->getValue() == 1)
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return DAG.getNode(ISD::OR, VT, N0, N2);
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// fold select C, 0, X -> ~C & X
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// FIXME: this should check for C type == X type, not i1?
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@ -1050,7 +1065,7 @@ SDOperand DAGCombiner::visitSELECT(SDNode *N) {
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return DAG.getNode(ISD::AND, VT, XORNode, N2);
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}
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// fold select C, X, 1 -> ~C | X
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if (MVT::i1 == VT && N2C && !N2C->isNullValue()) {
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if (MVT::i1 == VT && N2C && N2C->getValue() == 1) {
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SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
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WorkList.push_back(XORNode.Val);
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return DAG.getNode(ISD::OR, VT, XORNode, N1);
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@ -1065,12 +1080,40 @@ SDOperand DAGCombiner::visitSELECT(SDNode *N) {
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// fold X ? Y : X --> X ? Y : 0 --> X & Y
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if (MVT::i1 == VT && N0 == N2)
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return DAG.getNode(ISD::AND, VT, N0, N1);
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// fold selects based on a setcc into other things, such as min/max/abs
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if (N0.getOpcode() == ISD::SETCC)
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return SimplifySelect(N0, N1, N2);
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return SDOperand();
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}
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SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) {
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return SDOperand();
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SDOperand N0 = N->getOperand(0);
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SDOperand N1 = N->getOperand(1);
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SDOperand N2 = N->getOperand(2);
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SDOperand N3 = N->getOperand(3);
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SDOperand N4 = N->getOperand(4);
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ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
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ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
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ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
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ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
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// Determine if the condition we're dealing with is constant
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SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC);
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ConstantSDNode *SCCC = dyn_cast<ConstantSDNode>(SCC);
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bool constTrue = SCCC && SCCC->getValue() == 1;
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bool constFalse = SCCC && SCCC->isNullValue();
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// fold select_cc lhs, rhs, x, x, cc -> x
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if (N2 == N3)
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return N2;
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// fold select_cc true, x, y -> x
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if (constTrue)
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return N2;
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// fold select_cc false, x, y -> y
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if (constFalse)
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return N3;
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// fold select_cc into other things, such as min/max/abs
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return SimplifySelectCC(N0, N1, N2, N3, CC);
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}
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SDOperand DAGCombiner::visitSETCC(SDNode *N) {
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@ -1290,6 +1333,59 @@ SDOperand DAGCombiner::visitFABS(SDNode *N) {
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return SDOperand();
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}
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SDOperand DAGCombiner::visitBRCOND(SDNode *N) {
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SDOperand Chain = N->getOperand(0);
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SDOperand N1 = N->getOperand(1);
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SDOperand N2 = N->getOperand(2);
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ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
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// never taken branch, fold to chain
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if (N1C && N1C->isNullValue())
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return Chain;
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// unconditional branch
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if (N1C && !N1C->isNullValue())
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return DAG.getNode(ISD::BR, MVT::Other, Chain, N2);
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return SDOperand();
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}
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SDOperand DAGCombiner::visitBRCONDTWOWAY(SDNode *N) {
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SDOperand Chain = N->getOperand(0);
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SDOperand N1 = N->getOperand(1);
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SDOperand N2 = N->getOperand(2);
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SDOperand N3 = N->getOperand(3);
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ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
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// unconditional branch to true mbb
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if (N1C && N1C->getValue() == 1)
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return DAG.getNode(ISD::BR, MVT::Other, Chain, N2);
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// unconditional branch to false mbb
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if (N1C && N1C->isNullValue())
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return DAG.getNode(ISD::BR, MVT::Other, Chain, N3);
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return SDOperand();
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}
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SDOperand DAGCombiner::visitBR_CC(SDNode *N) {
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// FIXME: come up with a common way between br_cc, brtwoway_cc, and select_cc
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// to canonicalize the condition without calling getnode a bazillion times.
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return SDOperand();
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}
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SDOperand DAGCombiner::visitBRTWOWAY_CC(SDNode *N) {
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// FIXME: come up with a common way between br_cc, brtwoway_cc, and select_cc
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// to canonicalize the condition without calling getnode a bazillion times.
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return SDOperand();
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}
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SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){
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return SDOperand();
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}
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SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1,
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SDOperand N2, SDOperand N3,
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ISD::CondCode CC) {
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return SDOperand();
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}
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SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0,
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SDOperand N1, ISD::CondCode Cond) {
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// These setcc operations always fold.
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