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bool %test(int %X) {
  %Y = seteq int %X, 13
  ret bool %Y
}

as

_test:
        addi r2, r3, -13
        cntlzw r2, r2
        srwi r3, r2, 5
        blr

rather than

_test:
        cmpwi cr7, r3, 13
        mfcr r2
        rlwinm r3, r2, 31, 31, 31
        blr

This has very little effect on most code, but speeds up analyzer 23% and
mason 11%


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25848 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nate Begeman 2006-01-31 08:17:29 +00:00
parent a34b898bc0
commit 4477590ef6
1 changed files with 16 additions and 0 deletions
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16
lib/Target/PowerPC/PPCISelLowering.cpp
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@ -83,6 +83,9 @@ PPCTargetLowering::PPCTargetLowering(TargetMachine &TM)
// PowerPC wants to turn select_cc of FP into fsel when possible.
setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
// PowerPC wants to optimize setcc i32, imm a bit.
setOperationAction(ISD::SETCC, MVT::i32, Custom);
// PowerPC does not have BRCOND* which requires SetCC
setOperationAction(ISD::BRCOND, MVT::Other, Expand);
@ -445,6 +448,19 @@ SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
// resolution stub.
return DAG.getLoad(MVT::i32, DAG.getEntryNode(), Lo, DAG.getSrcValue(0));
}
case ISD::SETCC: {
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
if (C->getValue() && !C->isAllOnesValue())
if (CC == ISD::SETEQ || CC == ISD::SETNE ||
CC == ISD::SETLT || CC == ISD::SETGT) {
MVT::ValueType VT = Op.getValueType();
SDOperand SUB = DAG.getNode(ISD::SUB, Op.getOperand(0).getValueType(),
Op.getOperand(0), Op.getOperand(1));
return DAG.getSetCC(VT, SUB, DAG.getConstant(0, VT), CC);
}
break;
}
case ISD::VASTART: {
// vastart just stores the address of the VarArgsFrameIndex slot into the
// memory location argument.