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Notes about codegen issues.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35107 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2007-03-14 21:03:53 +00:00
parent edd174bcca
commit 4485d3897b
1 changed files with 47 additions and 0 deletions
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47
lib/Target/X86/README.txt
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@ -339,6 +339,53 @@ lambda, siod, optimizer-eval, ackermann, hash2, nestedloop, strcat, and Treesor.
//===---------------------------------------------------------------------===//
We are generating far worse code than gcc:
volatile short X, Y;
void foo(int N) {
int i;
for (i = 0; i < N; i++) { X = i; Y = i*4; }
}
LBB1_1: #bb.preheader
xorl %ecx, %ecx
xorw %dx, %dx
LBB1_2: #bb
movl L_X$non_lazy_ptr, %esi
movw %dx, (%esi)
movw %dx, %si
shlw $2, %si
movl L_Y$non_lazy_ptr, %edi
movw %si, (%edi)
incl %ecx
incw %dx
cmpl %eax, %ecx
jne LBB1_2 #bb
vs.
xorl %edx, %edx
movl L_X$non_lazy_ptr-"L00000000001$pb"(%ebx), %esi
movl L_Y$non_lazy_ptr-"L00000000001$pb"(%ebx), %ecx
L4:
movw %dx, (%esi)
leal 0(,%edx,4), %eax
movw %ax, (%ecx)
addl $1, %edx
cmpl %edx, %edi
jne L4
There are 3 issues:
1. Lack of post regalloc LICM.
2. Poor sub-regclass support. That leads to inability to promote the 16-bit
arithmetic op to 32-bit and making use of leal.
3. LSR unable to reused IV for a different type (i16 vs. i32) even though
the cast would be free.
//===---------------------------------------------------------------------===//
Teach the coalescer to coalesce vregs of different register classes. e.g. FR32 /
FR64 to VR128.