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Notes about codegen issues.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35107 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -339,6 +339,53 @@ lambda, siod, optimizer-eval, ackermann, hash2, nestedloop, strcat, and Treesor.
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//===---------------------------------------------------------------------===//
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We are generating far worse code than gcc:
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volatile short X, Y;
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void foo(int N) {
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int i;
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for (i = 0; i < N; i++) { X = i; Y = i*4; }
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}
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LBB1_1: #bb.preheader
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xorl %ecx, %ecx
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xorw %dx, %dx
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LBB1_2: #bb
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movl L_X$non_lazy_ptr, %esi
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movw %dx, (%esi)
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movw %dx, %si
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shlw $2, %si
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movl L_Y$non_lazy_ptr, %edi
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movw %si, (%edi)
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incl %ecx
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incw %dx
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cmpl %eax, %ecx
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jne LBB1_2 #bb
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vs.
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xorl %edx, %edx
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movl L_X$non_lazy_ptr-"L00000000001$pb"(%ebx), %esi
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movl L_Y$non_lazy_ptr-"L00000000001$pb"(%ebx), %ecx
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L4:
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movw %dx, (%esi)
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leal 0(,%edx,4), %eax
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movw %ax, (%ecx)
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addl $1, %edx
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cmpl %edx, %edi
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jne L4
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There are 3 issues:
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1. Lack of post regalloc LICM.
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2. Poor sub-regclass support. That leads to inability to promote the 16-bit
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arithmetic op to 32-bit and making use of leal.
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3. LSR unable to reused IV for a different type (i16 vs. i32) even though
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the cast would be free.
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//===---------------------------------------------------------------------===//
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Teach the coalescer to coalesce vregs of different register classes. e.g. FR32 /
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FR64 to VR128.
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