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Whitespace and 80-col cleanup.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77718 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eric Christopher 2009-07-31 20:07:27 +00:00
parent 84a832f927
commit 44b93ff9ad
1 changed files with 167 additions and 153 deletions
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70
lib/Target/X86/X86InstrSSE.td
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@ -432,12 +432,14 @@ def UCOMISSrm: PSI<0x2E, MRMSrcMem, (outs), (ins FR32:$src1, f32mem:$src2),
// Aliases to match intrinsics which expect XMM operand(s). // Aliases to match intrinsics which expect XMM operand(s).
let Constraints = "$src1 = $dst" in { let Constraints = "$src1 = $dst" in {
def Int_CMPSSrr : SSIi8<0xC2, MRMSrcReg, def Int_CMPSSrr : SSIi8<0xC2, MRMSrcReg,
(outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc), (outs VR128:$dst), (ins VR128:$src1, VR128:$src,
SSECC:$cc),
"cmp${cc}ss\t{$src, $dst|$dst, $src}", "cmp${cc}ss\t{$src, $dst|$dst, $src}",
[(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1, [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
VR128:$src, imm:$cc))]>; VR128:$src, imm:$cc))]>;
def Int_CMPSSrm : SSIi8<0xC2, MRMSrcMem, def Int_CMPSSrm : SSIi8<0xC2, MRMSrcMem,
(outs VR128:$dst), (ins VR128:$src1, f32mem:$src, SSECC:$cc), (outs VR128:$dst), (ins VR128:$src1, f32mem:$src,
SSECC:$cc),
"cmp${cc}ss\t{$src, $dst|$dst, $src}", "cmp${cc}ss\t{$src, $dst|$dst, $src}",
[(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1, [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
(load addr:$src), imm:$cc))]>; (load addr:$src), imm:$cc))]>;
@ -463,8 +465,8 @@ def Int_COMISSrm: PSI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
(implicit EFLAGS)]>; (implicit EFLAGS)]>;
} // Defs = [EFLAGS] } // Defs = [EFLAGS]
// Aliases of packed SSE1 instructions for scalar use. These all have names that // Aliases of packed SSE1 instructions for scalar use. These all have names
// start with 'Fs'. // that start with 'Fs'.
// Alias instructions that map fld0 to pxor for sse. // Alias instructions that map fld0 to pxor for sse.
let isReMaterializable = 1, isAsCheapAsAMove = 1 in let isReMaterializable = 1, isAsCheapAsAMove = 1 in
@ -1054,9 +1056,9 @@ def MOVZSS2PSrm : SSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f32mem:$src),
def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))), def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
(MOVZSS2PSrm addr:$src)>; (MOVZSS2PSrm addr:$src)>;
//===----------------------------------------------------------------------===// //===---------------------------------------------------------------------===//
// SSE2 Instructions // SSE2 Instructions
//===----------------------------------------------------------------------===// //===---------------------------------------------------------------------===//
// Move Instructions // Move Instructions
let neverHasSideEffects = 1 in let neverHasSideEffects = 1 in
@ -1166,12 +1168,14 @@ def UCOMISDrm: PDI<0x2E, MRMSrcMem, (outs), (ins FR64:$src1, f64mem:$src2),
// Aliases to match intrinsics which expect XMM operand(s). // Aliases to match intrinsics which expect XMM operand(s).
let Constraints = "$src1 = $dst" in { let Constraints = "$src1 = $dst" in {
def Int_CMPSDrr : SDIi8<0xC2, MRMSrcReg, def Int_CMPSDrr : SDIi8<0xC2, MRMSrcReg,
(outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc), (outs VR128:$dst), (ins VR128:$src1, VR128:$src,
SSECC:$cc),
"cmp${cc}sd\t{$src, $dst|$dst, $src}", "cmp${cc}sd\t{$src, $dst|$dst, $src}",
[(set VR128:$dst, (int_x86_sse2_cmp_sd VR128:$src1, [(set VR128:$dst, (int_x86_sse2_cmp_sd VR128:$src1,
VR128:$src, imm:$cc))]>; VR128:$src, imm:$cc))]>;
def Int_CMPSDrm : SDIi8<0xC2, MRMSrcMem, def Int_CMPSDrm : SDIi8<0xC2, MRMSrcMem,
(outs VR128:$dst), (ins VR128:$src1, f64mem:$src, SSECC:$cc), (outs VR128:$dst), (ins VR128:$src1, f64mem:$src,
SSECC:$cc),
"cmp${cc}sd\t{$src, $dst|$dst, $src}", "cmp${cc}sd\t{$src, $dst|$dst, $src}",
[(set VR128:$dst, (int_x86_sse2_cmp_sd VR128:$src1, [(set VR128:$dst, (int_x86_sse2_cmp_sd VR128:$src1,
(load addr:$src), imm:$cc))]>; (load addr:$src), imm:$cc))]>;
@ -1197,8 +1201,8 @@ def Int_COMISDrm: PDI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
(implicit EFLAGS)]>; (implicit EFLAGS)]>;
} // Defs = [EFLAGS] } // Defs = [EFLAGS]
// Aliases of packed SSE2 instructions for scalar use. These all have names that // Aliases of packed SSE2 instructions for scalar use. These all have names
// start with 'Fs'. // that start with 'Fs'.
// Alias instructions that map fld0 to pxor for sse. // Alias instructions that map fld0 to pxor for sse.
let isReMaterializable = 1, isAsCheapAsAMove = 1 in let isReMaterializable = 1, isAsCheapAsAMove = 1 in
@ -1405,7 +1409,7 @@ defm MAX : sse2_fp_binop_rm<0x5F, "max", X86fmax,
defm MIN : sse2_fp_binop_rm<0x5D, "min", X86fmin, defm MIN : sse2_fp_binop_rm<0x5D, "min", X86fmin,
int_x86_sse2_min_sd, int_x86_sse2_min_pd>; int_x86_sse2_min_sd, int_x86_sse2_min_pd>;
//===----------------------------------------------------------------------===// //===---------------------------------------------------------------------===//
// SSE packed FP Instructions // SSE packed FP Instructions
// Move Instructions // Move Instructions
@ -1773,7 +1777,7 @@ let Constraints = "$src1 = $dst" in {
} // Constraints = "$src1 = $dst" } // Constraints = "$src1 = $dst"
//===----------------------------------------------------------------------===// //===---------------------------------------------------------------------===//
// SSE integer instructions // SSE integer instructions
// Move Instructions // Move Instructions
@ -1828,14 +1832,17 @@ multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
multiclass PDI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm, multiclass PDI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
string OpcodeStr, string OpcodeStr,
Intrinsic IntId, Intrinsic IntId2> { Intrinsic IntId, Intrinsic IntId2> {
def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1,
VR128:$src2),
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
[(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>; [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2), def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1,
i128mem:$src2),
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
[(set VR128:$dst, (IntId VR128:$src1, [(set VR128:$dst, (IntId VR128:$src1,
(bitconvert (memopv2i64 addr:$src2))))]>; (bitconvert (memopv2i64 addr:$src2))))]>;
def ri : PDIi8<opc2, ImmForm, (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2), def ri : PDIi8<opc2, ImmForm, (outs VR128:$dst), (ins VR128:$src1,
i32i8imm:$src2),
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
[(set VR128:$dst, (IntId2 VR128:$src1, (i32 imm:$src2)))]>; [(set VR128:$dst, (IntId2 VR128:$src1, (i32 imm:$src2)))]>;
} }
@ -1843,12 +1850,14 @@ multiclass PDI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
/// PDI_binop_rm - Simple SSE2 binary operator. /// PDI_binop_rm - Simple SSE2 binary operator.
multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode, multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
ValueType OpVT, bit Commutable = 0> { ValueType OpVT, bit Commutable = 0> {
def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1,
VR128:$src2),
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
[(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]> { [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]> {
let isCommutable = Commutable; let isCommutable = Commutable;
} }
def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2), def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1,
i128mem:$src2),
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
[(set VR128:$dst, (OpVT (OpNode VR128:$src1, [(set VR128:$dst, (OpVT (OpNode VR128:$src1,
(bitconvert (memopv2i64 addr:$src2)))))]>; (bitconvert (memopv2i64 addr:$src2)))))]>;
@ -1861,14 +1870,17 @@ multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
/// ///
multiclass PDI_binop_rm_v2i64<bits<8> opc, string OpcodeStr, SDNode OpNode, multiclass PDI_binop_rm_v2i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
bit Commutable = 0> { bit Commutable = 0> {
def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
(ins VR128:$src1, VR128:$src2),
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
[(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))]> { [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))]> {
let isCommutable = Commutable; let isCommutable = Commutable;
} }
def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2), def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
(ins VR128:$src1, i128mem:$src2),
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
[(set VR128:$dst, (OpNode VR128:$src1,(memopv2i64 addr:$src2)))]>; [(set VR128:$dst, (OpNode VR128:$src1,
(memopv2i64 addr:$src2)))]>;
} }
} // Constraints = "$src1 = $dst" } // Constraints = "$src1 = $dst"
@ -2402,9 +2414,9 @@ def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4i32 addr:$src)))),
(MOVZPQILo2PQIrm addr:$src)>; (MOVZPQILo2PQIrm addr:$src)>;
} }
//===----------------------------------------------------------------------===// //===---------------------------------------------------------------------===//
// SSE3 Instructions // SSE3 Instructions
//===----------------------------------------------------------------------===// //===---------------------------------------------------------------------===//
// Move Instructions // Move Instructions
def MOVSHDUPrr : S3SI<0x16, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), def MOVSHDUPrr : S3SI<0x16, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
@ -2528,9 +2540,9 @@ let AddedComplexity = 20 in
def : Pat<(v4i32 (movsldup (bc_v4i32 (memopv2i64 addr:$src)), (undef))), def : Pat<(v4i32 (movsldup (bc_v4i32 (memopv2i64 addr:$src)), (undef))),
(MOVSLDUPrm addr:$src)>, Requires<[HasSSE3]>; (MOVSLDUPrm addr:$src)>, Requires<[HasSSE3]>;
//===----------------------------------------------------------------------===// //===---------------------------------------------------------------------===//
// SSSE3 Instructions // SSSE3 Instructions
//===----------------------------------------------------------------------===// //===---------------------------------------------------------------------===//
/// SS3I_unop_rm_int_8 - Simple SSSE3 unary operator whose type is v*i8. /// SS3I_unop_rm_int_8 - Simple SSSE3 unary operator whose type is v*i8.
multiclass SS3I_unop_rm_int_8<bits<8> opc, string OpcodeStr, multiclass SS3I_unop_rm_int_8<bits<8> opc, string OpcodeStr,
@ -2804,12 +2816,13 @@ def : Pat<(X86pshufb VR128:$src, VR128:$mask),
def : Pat<(X86pshufb VR128:$src, (bc_v16i8 (memopv2i64 addr:$mask))), def : Pat<(X86pshufb VR128:$src, (bc_v16i8 (memopv2i64 addr:$mask))),
(PSHUFBrm128 VR128:$src, addr:$mask)>, Requires<[HasSSSE3]>; (PSHUFBrm128 VR128:$src, addr:$mask)>, Requires<[HasSSSE3]>;
//===----------------------------------------------------------------------===// //===---------------------------------------------------------------------===//
// Non-Instruction Patterns // Non-Instruction Patterns
//===----------------------------------------------------------------------===// //===---------------------------------------------------------------------===//
// extload f32 -> f64. This matches load+fextend because we have a hack in // extload f32 -> f64. This matches load+fextend because we have a hack in
// the isel (PreprocessForFPConvert) that can introduce loads after dag combine. // the isel (PreprocessForFPConvert) that can introduce loads after dag
// combine.
// Since these loads aren't folded into the fextend, we have to match it // Since these loads aren't folded into the fextend, we have to match it
// explicitly here. // explicitly here.
let Predicates = [HasSSE2] in let Predicates = [HasSSE2] in
@ -3604,7 +3617,8 @@ let Constraints = "$src1 = $dst" in {
!strconcat(OpcodeStr, !strconcat(OpcodeStr,
"\t{$src3, $src2, $dst|$dst, $src2, $src3}"), "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
[(set VR128:$dst, [(set VR128:$dst,
(X86insrtps VR128:$src1, VR128:$src2, imm:$src3))]>, OpSize; (X86insrtps VR128:$src1, VR128:$src2, imm:$src3))]>,
OpSize;
def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst), def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
(ins VR128:$src1, f32mem:$src2, i32i8imm:$src3), (ins VR128:$src1, f32mem:$src2, i32i8imm:$src3),
!strconcat(OpcodeStr, !strconcat(OpcodeStr,