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Extract the lower 64-bit if a MMX value is passed in a XMM register.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50292 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2008-04-25 20:13:28 +00:00
parent 082948df9b
commit 44c0fd17e1
1 changed files with 9 additions and 3 deletions
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12
lib/Target/X86/X86ISelLowering.cpp
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@ -1248,9 +1248,15 @@ X86TargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) {
ArgValue = DAG.getNode(ISD::TRUNCATE, VA.getValVT(), ArgValue);
// Handle MMX values passed in GPRs.
if (Is64Bit && RegVT != VA.getLocVT() && RC == X86::GR64RegisterClass &&
MVT::getSizeInBits(RegVT) == 64)
ArgValue = DAG.getNode(ISD::BIT_CONVERT, VA.getLocVT(), ArgValue);
if (Is64Bit && RegVT != VA.getLocVT()) {
if (MVT::getSizeInBits(RegVT) == 64 && RC == X86::GR64RegisterClass)
ArgValue = DAG.getNode(ISD::BIT_CONVERT, VA.getLocVT(), ArgValue);
else if (RC == X86::VR128RegisterClass) {
ArgValue = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i64, ArgValue,
DAG.getConstant(0, MVT::i64));
ArgValue = DAG.getNode(ISD::BIT_CONVERT, VA.getLocVT(), ArgValue);
}
}
ArgValues.push_back(ArgValue);
} else {