diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 8a8161925b9..9503bc13c48 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -221,7 +221,9 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
   } else {
     // Set up the FP register classes.
     addRegisterClass(MVT::f64, X86::RFPRegisterClass);
-
+    
+    setOperationAction(ISD::UNDEF, MVT::f64, Expand);
+    
     if (!X86PatIsel) {
       setOperationAction(ISD::SINT_TO_FP, MVT::i16, Custom);
       setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td
index 8362a7e6613..b3941b4fc57 100644
--- a/lib/Target/X86/X86InstrInfo.td
+++ b/lib/Target/X86/X86InstrInfo.td
@@ -3022,10 +3022,6 @@ def : Pat<(X86fst RFP:$src, addr:$op, f64), (FpST64m addr:$op, RFP:$src)>;
 def : Pat<(f64 fp64immneg0), (FpCHS (FpLD0))>, Requires<[FPStack]>;
 def : Pat<(f64 fp64immneg1), (FpCHS (FpLD1))>, Requires<[FPStack]>;
 
-// RFP undef
-def : Pat<(f64 (undef)), (FpLD0)>,  Requires<[FPStack]>;
-
-
 //===----------------------------------------------------------------------===//
 // Some peepholes
 //===----------------------------------------------------------------------===//