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Enable support for materializing i1, i8, and i16 integers via move immediate.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143739 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chad Rosier 2011-11-04 22:29:00 +00:00
parent a0dd4cbc87
commit 44e895761f
1 changed files with 11 additions and 6 deletions
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17
lib/Target/ARM/ARMFastISel.cpp
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@ -545,22 +545,27 @@ unsigned ARMFastISel::ARMMaterializeFP(const ConstantFP *CFP, EVT VT) {
unsigned ARMFastISel::ARMMaterializeInt(const Constant *C, EVT VT) {
// For now 32-bit only.
if (VT != MVT::i32) return false;
unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 && VT != MVT::i1)
return false;
// If we can do this in a single instruction without a constant pool entry
// do so now.
const ConstantInt *CI = cast<ConstantInt>(C);
if (Subtarget->hasV6T2Ops() && isUInt<16>(CI->getSExtValue())) {
unsigned Opc = isThumb ? ARM::t2MOVi16 : ARM::MOVi16;
unsigned ImmReg = createResultReg(TLI.getRegClassFor(VT));
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
TII.get(Opc), DestReg)
TII.get(Opc), ImmReg)
.addImm(CI->getSExtValue()));
return DestReg;
return ImmReg;
}
// For now 32-bit only.
if (VT != MVT::i32)
return false;
unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
// MachineConstantPool wants an explicit alignment.
unsigned Align = TD.getPrefTypeAlignment(C->getType());
if (Align == 0) {