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Scrap a huge layer of cruft out of this interface.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11980 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -36,9 +36,6 @@ class MachineCodeForInstruction;
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typedef short MachineOpCode;
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typedef unsigned InstrSchedClass;
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const MachineOpCode INVALID_MACHINE_OPCODE = -1;
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//---------------------------------------------------------------------------
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// struct TargetInstrDescriptor:
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// Predefined information about each machine instruction.
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@ -49,14 +46,8 @@ const unsigned M_NOP_FLAG = 1 << 0;
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const unsigned M_BRANCH_FLAG = 1 << 1;
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const unsigned M_CALL_FLAG = 1 << 2;
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const unsigned M_RET_FLAG = 1 << 3;
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const unsigned M_ARITH_FLAG = 1 << 4;
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const unsigned M_CC_FLAG = 1 << 6;
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const unsigned M_LOGICAL_FLAG = 1 << 6;
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const unsigned M_INT_FLAG = 1 << 7;
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const unsigned M_FLOAT_FLAG = 1 << 8;
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const unsigned M_CONDL_FLAG = 1 << 9;
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const unsigned M_LOAD_FLAG = 1 << 10;
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const unsigned M_PREFETCH_FLAG = 1 << 11;
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const unsigned M_STORE_FLAG = 1 << 12;
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const unsigned M_DUMMY_PHI_FLAG = 1 << 13;
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const unsigned M_PSEUDO_FLAG = 1 << 14; // Pseudo instruction
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@ -124,13 +115,6 @@ public:
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return get(opCode).numOperands;
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}
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int getResultPos(MachineOpCode opCode) const {
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return get(opCode).resultPos;
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}
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unsigned getNumDelaySlots(MachineOpCode opCode) const {
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return get(opCode).numDelaySlots;
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}
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InstrSchedClass getSchedClass(MachineOpCode opCode) const {
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return get(opCode).schedClass;
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@ -144,66 +128,15 @@ public:
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return get(opCode).ImplicitDefs;
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}
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//
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// Query instruction class flags according to the machine-independent
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// flags listed above.
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//
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bool isNop(MachineOpCode opCode) const {
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return get(opCode).Flags & M_NOP_FLAG;
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}
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bool isBranch(MachineOpCode opCode) const {
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return get(opCode).Flags & M_BRANCH_FLAG;
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}
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bool isCall(MachineOpCode opCode) const {
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return get(opCode).Flags & M_CALL_FLAG;
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}
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bool isReturn(MachineOpCode opCode) const {
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return get(opCode).Flags & M_RET_FLAG;
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}
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bool isControlFlow(MachineOpCode opCode) const {
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return get(opCode).Flags & M_BRANCH_FLAG
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|| get(opCode).Flags & M_CALL_FLAG
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|| get(opCode).Flags & M_RET_FLAG;
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}
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bool isArith(MachineOpCode opCode) const {
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return get(opCode).Flags & M_ARITH_FLAG;
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}
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bool isCCInstr(MachineOpCode opCode) const {
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return get(opCode).Flags & M_CC_FLAG;
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}
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bool isLogical(MachineOpCode opCode) const {
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return get(opCode).Flags & M_LOGICAL_FLAG;
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}
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bool isIntInstr(MachineOpCode opCode) const {
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return get(opCode).Flags & M_INT_FLAG;
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}
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bool isFloatInstr(MachineOpCode opCode) const {
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return get(opCode).Flags & M_FLOAT_FLAG;
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}
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bool isConditional(MachineOpCode opCode) const {
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return get(opCode).Flags & M_CONDL_FLAG;
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}
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bool isLoad(MachineOpCode opCode) const {
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return get(opCode).Flags & M_LOAD_FLAG;
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}
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bool isPrefetch(MachineOpCode opCode) const {
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return get(opCode).Flags & M_PREFETCH_FLAG;
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}
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bool isLoadOrPrefetch(MachineOpCode opCode) const {
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return get(opCode).Flags & M_LOAD_FLAG
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|| get(opCode).Flags & M_PREFETCH_FLAG;
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}
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bool isStore(MachineOpCode opCode) const {
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return get(opCode).Flags & M_STORE_FLAG;
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}
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bool isMemoryAccess(MachineOpCode opCode) const {
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return get(opCode).Flags & M_LOAD_FLAG
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|| get(opCode).Flags & M_PREFETCH_FLAG
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|| get(opCode).Flags & M_STORE_FLAG;
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}
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bool isDummyPhiInstr(MachineOpCode opCode) const {
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return get(opCode).Flags & M_DUMMY_PHI_FLAG;
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}
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bool isPseudoInstr(MachineOpCode opCode) const {
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return get(opCode).Flags & M_PSEUDO_FLAG;
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}
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@ -224,6 +157,45 @@ public:
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return false;
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}
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//-------------------------------------------------------------------------
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// Code generation support for creating individual machine instructions
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//
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// WARNING: These methods are Sparc specific
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//
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// DO NOT USE ANY OF THESE METHODS THEY ARE DEPRECATED!
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//
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//-------------------------------------------------------------------------
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int getResultPos(MachineOpCode opCode) const {
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return get(opCode).resultPos;
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}
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unsigned getNumDelaySlots(MachineOpCode opCode) const {
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return get(opCode).numDelaySlots;
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}
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bool isCCInstr(MachineOpCode opCode) const {
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return get(opCode).Flags & M_CC_FLAG;
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}
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bool isNop(MachineOpCode opCode) const {
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return get(opCode).Flags & M_NOP_FLAG;
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}
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bool isBranch(MachineOpCode opCode) const {
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return get(opCode).Flags & M_BRANCH_FLAG;
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}
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bool isCall(MachineOpCode opCode) const {
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return get(opCode).Flags & M_CALL_FLAG;
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}
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bool isLoad(MachineOpCode opCode) const {
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return get(opCode).Flags & M_LOAD_FLAG;
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}
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bool isStore(MachineOpCode opCode) const {
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return get(opCode).Flags & M_STORE_FLAG;
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}
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bool isDummyPhiInstr(MachineOpCode opCode) const {
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return get(opCode).Flags & M_DUMMY_PHI_FLAG;
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}
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// Check if an instruction can be issued before its operands are ready,
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// or if a subsequent instruction that uses its result can be issued
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// before the results are ready.
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@ -232,7 +204,6 @@ public:
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virtual bool hasOperandInterlock(MachineOpCode opCode) const {
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return true;
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}
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virtual bool hasResultInterlock(MachineOpCode opCode) const {
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return true;
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}
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@ -292,26 +263,6 @@ public:
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return true; // safe but very conservative
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}
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/// createNOPinstr - returns the target's implementation of NOP, which is
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/// usually a pseudo-instruction, implemented by a degenerate version of
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/// another instruction, e.g. X86: xchg ax, ax; SparcV9: sethi g0, 0
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///
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virtual MachineInstr* createNOPinstr() const = 0;
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/// isNOPinstr - not having a special NOP opcode, we need to know if a given
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/// instruction is interpreted as an `official' NOP instr, i.e., there may be
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/// more than one way to `do nothing' but only one canonical way to slack off.
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///
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virtual bool isNOPinstr(const MachineInstr &MI) const = 0;
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//-------------------------------------------------------------------------
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// Code generation support for creating individual machine instructions
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//
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// WARNING: These methods are Sparc specific
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//
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//-------------------------------------------------------------------------
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// Get certain common op codes for the current target. this and all the
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// Create* methods below should be moved to a machine code generation class
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//
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