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MIPS DSP: CMPU.EQ.QB instruction sub-class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164755 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka
parent
a216401621
commit
451b0e7b8a
@ -57,6 +57,48 @@ class RADDU_W_QB_FMT<bits<5> op> : DSPInst {
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let Inst{5-0} = 0b010000;
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}
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// CMPU.EQ.QB sub-class format.
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class CMP_EQ_QB_R2_FMT<bits<5> op> : DSPInst {
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bits<5> rs;
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bits<5> rt;
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let Opcode = SPECIAL3_OPCODE.V;
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let Inst{25-21} = rs;
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let Inst{20-16} = rt;
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let Inst{15-11} = 0;
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let Inst{10-6} = op;
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let Inst{5-0} = 0b010001;
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}
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class CMP_EQ_QB_R3_FMT<bits<5> op> : DSPInst {
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bits<5> rs;
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bits<5> rt;
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bits<5> rd;
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let Opcode = SPECIAL3_OPCODE.V;
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let Inst{25-21} = rs;
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let Inst{20-16} = rt;
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let Inst{15-11} = rd;
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let Inst{10-6} = op;
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let Inst{5-0} = 0b010001;
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}
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class PRECR_SRA_PH_W_FMT<bits<5> op> : DSPInst {
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bits<5> rs;
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bits<5> rt;
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bits<5> sa;
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let Opcode = SPECIAL3_OPCODE.V;
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let Inst{25-21} = rs;
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let Inst{20-16} = rt;
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let Inst{15-11} = sa;
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let Inst{10-6} = op;
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let Inst{5-0} = 0b010001;
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}
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// DPA.W.PH sub-class format.
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class DPA_W_PH_FMT<bits<5> op> : DSPInst {
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bits<2> ac;
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@ -106,6 +106,10 @@ class ADDSC_ENC : ADDU_QB_FMT<0b10000>;
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class ADDWC_ENC : ADDU_QB_FMT<0b10001>;
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class MODSUB_ENC : ADDU_QB_FMT<0b10010>;
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class RADDU_W_QB_ENC : RADDU_W_QB_FMT<0b10100>;
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class PRECRQ_QB_PH_ENC : CMP_EQ_QB_R3_FMT<0b01100>;
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class PRECRQ_PH_W_ENC : CMP_EQ_QB_R3_FMT<0b10100>;
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class PRECRQ_RS_PH_W_ENC : CMP_EQ_QB_R3_FMT<0b10101>;
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class PRECRQU_S_QB_PH_ENC : CMP_EQ_QB_R3_FMT<0b01111>;
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class MULEU_S_PH_QBL_ENC : ADDU_QB_FMT<0b00110>;
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class MULEU_S_PH_QBR_ENC : ADDU_QB_FMT<0b00111>;
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class MULEQ_S_W_PHL_ENC : ADDU_QB_FMT<0b11100>;
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@ -130,6 +134,18 @@ class MADD_DSP_ENC : MULT_FMT<0b011100, 0b000000>;
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class MADDU_DSP_ENC : MULT_FMT<0b011100, 0b000001>;
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class MSUB_DSP_ENC : MULT_FMT<0b011100, 0b000100>;
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class MSUBU_DSP_ENC : MULT_FMT<0b011100, 0b000101>;
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class CMPU_EQ_QB_ENC : CMP_EQ_QB_R2_FMT<0b00000>;
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class CMPU_LT_QB_ENC : CMP_EQ_QB_R2_FMT<0b00001>;
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class CMPU_LE_QB_ENC : CMP_EQ_QB_R2_FMT<0b00010>;
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class CMPGU_EQ_QB_ENC : CMP_EQ_QB_R3_FMT<0b00100>;
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class CMPGU_LT_QB_ENC : CMP_EQ_QB_R3_FMT<0b00101>;
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class CMPGU_LE_QB_ENC : CMP_EQ_QB_R3_FMT<0b00110>;
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class CMP_EQ_PH_ENC : CMP_EQ_QB_R2_FMT<0b01000>;
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class CMP_LT_PH_ENC : CMP_EQ_QB_R2_FMT<0b01001>;
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class CMP_LE_PH_ENC : CMP_EQ_QB_R2_FMT<0b01010>;
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class PACKRL_PH_ENC : CMP_EQ_QB_R3_FMT<0b01110>;
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class PICK_QB_ENC : CMP_EQ_QB_R3_FMT<0b00011>;
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class PICK_PH_ENC : CMP_EQ_QB_R3_FMT<0b01011>;
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class BPOSGE32_ENC : BPOSGE32_FMT<0b11100>;
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class EXTP_ENC : EXTR_W_TY1_FMT<0b00010>;
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@ -152,6 +168,9 @@ class ADDU_PH_ENC : ADDU_QB_FMT<0b01000>;
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class ADDU_S_PH_ENC : ADDU_QB_FMT<0b01100>;
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class SUBU_PH_ENC : ADDU_QB_FMT<0b01001>;
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class SUBU_S_PH_ENC : ADDU_QB_FMT<0b01101>;
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class CMPGDU_EQ_QB_ENC : CMP_EQ_QB_R3_FMT<0b11000>;
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class CMPGDU_LT_QB_ENC : CMP_EQ_QB_R3_FMT<0b11001>;
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class CMPGDU_LE_QB_ENC : CMP_EQ_QB_R3_FMT<0b11010>;
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class MULQ_S_PH_ENC : ADDU_QB_FMT<0b11110>;
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class DPA_W_PH_ENC : DPA_W_PH_FMT<0b00000>;
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class DPS_W_PH_ENC : DPA_W_PH_FMT<0b00001>;
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@ -162,6 +181,9 @@ class DPSX_W_PH_ENC : DPA_W_PH_FMT<0b01001>;
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class DPSQX_S_W_PH_ENC : DPA_W_PH_FMT<0b11001>;
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class DPSQX_SA_W_PH_ENC : DPA_W_PH_FMT<0b11011>;
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class MULSA_W_PH_ENC : DPA_W_PH_FMT<0b00010>;
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class PRECR_QB_PH_ENC : CMP_EQ_QB_R3_FMT<0b01101>;
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class PRECR_SRA_PH_W_ENC : PRECR_SRA_PH_W_FMT<0b11110>;
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class PRECR_SRA_R_PH_W_ENC : PRECR_SRA_PH_W_FMT<0b11111>;
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// Instruction desc.
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class ADDU_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
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@ -186,6 +208,40 @@ class RADDU_W_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
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list<Register> Defs = [DSPCtrl];
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}
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class CMP_EQ_QB_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
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InstrItinClass itin, RegisterClass RCS,
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RegisterClass RCT = RCS> {
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dag OutOperandList = (outs);
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dag InOperandList = (ins RCS:$rs, RCT:$rt);
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string AsmString = !strconcat(instr_asm, "\t$rs, $rt");
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list<dag> Pattern = [(OpNode RCS:$rs, RCT:$rt)];
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InstrItinClass Itinerary = itin;
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list<Register> Defs = [DSPCtrl];
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}
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class CMP_EQ_QB_R3_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
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InstrItinClass itin, RegisterClass RCD,
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RegisterClass RCS, RegisterClass RCT = RCS> {
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dag OutOperandList = (outs RCD:$rd);
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dag InOperandList = (ins RCS:$rs, RCT:$rt);
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string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
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list<dag> Pattern = [(set RCD:$rd, (OpNode RCS:$rs, RCT:$rt))];
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InstrItinClass Itinerary = itin;
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list<Register> Defs = [DSPCtrl];
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}
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class PRECR_SRA_PH_W_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
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InstrItinClass itin, RegisterClass RCT,
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RegisterClass RCS = RCT> {
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dag OutOperandList = (outs RCT:$rt);
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dag InOperandList = (ins RCS:$rs, shamt:$sa, RCS:$src);
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string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $sa");
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list<dag> Pattern = [(set RCT:$rt, (OpNode RCS:$src, RCS:$rs, immZExt5:$sa))];
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InstrItinClass Itinerary = itin;
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list<Register> Defs = [DSPCtrl];
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string Constraints = "$src = $rt";
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}
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class EXTR_W_TY1_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
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InstrItinClass itin> {
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dag OutOperandList = (outs CPURegs:$rt);
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@ -340,6 +396,27 @@ class RADDU_W_QB_DESC : RADDU_W_QB_DESC_BASE<"raddu.w.qb", int_mips_raddu_w_qb,
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NoItinerary, CPURegs, DSPRegs>,
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ClearDefs;
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// Precision reduce/expand
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class PRECRQ_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq.qb.ph",
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int_mips_precrq_qb_ph,
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NoItinerary, DSPRegs, DSPRegs>,
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ClearDefs;
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class PRECRQ_PH_W_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq.ph.w",
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int_mips_precrq_ph_w,
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NoItinerary, DSPRegs, CPURegs>,
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ClearDefs;
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class PRECRQ_RS_PH_W_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq_rs.ph.w",
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int_mips_precrq_rs_ph_w,
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NoItinerary, DSPRegs,
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CPURegs>;
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class PRECRQU_S_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrqu_s.qb.ph",
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int_mips_precrqu_s_qb_ph,
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NoItinerary, DSPRegs,
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DSPRegs>;
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// Multiplication
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class MULEU_S_PH_QBL_DESC : ADDU_QB_DESC_BASE<"muleu_s.ph.qbl",
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int_mips_muleu_s_ph_qbl,
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@ -402,7 +479,59 @@ class MSUB_DSP_DESC : MULT_DESC_BASE<"msub">;
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class MSUBU_DSP_DESC : MULT_DESC_BASE<"msubu">;
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// Comparison
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class CMPU_EQ_QB_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmpu.eq.qb",
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int_mips_cmpu_eq_qb, NoItinerary,
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DSPRegs>, IsCommutable;
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class CMPU_LT_QB_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmpu.lt.qb",
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int_mips_cmpu_lt_qb, NoItinerary,
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DSPRegs>, IsCommutable;
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class CMPU_LE_QB_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmpu.le.qb",
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int_mips_cmpu_le_qb, NoItinerary,
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DSPRegs>, IsCommutable;
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class CMPGU_EQ_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgu.eq.qb",
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int_mips_cmpgu_eq_qb,
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NoItinerary, CPURegs, DSPRegs>,
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IsCommutable;
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class CMPGU_LT_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgu.lt.qb",
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int_mips_cmpgu_lt_qb,
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NoItinerary, CPURegs, DSPRegs>,
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IsCommutable;
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class CMPGU_LE_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgu.le.qb",
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int_mips_cmpgu_le_qb,
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NoItinerary, CPURegs, DSPRegs>,
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IsCommutable;
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class CMP_EQ_PH_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmp.eq.ph", int_mips_cmp_eq_ph,
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NoItinerary, DSPRegs>,
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IsCommutable;
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class CMP_LT_PH_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmp.lt.ph", int_mips_cmp_lt_ph,
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NoItinerary, DSPRegs>,
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IsCommutable;
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class CMP_LE_PH_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmp.le.ph", int_mips_cmp_le_ph,
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NoItinerary, DSPRegs>,
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IsCommutable;
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// Misc
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class PACKRL_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"packrl.ph", int_mips_packrl_ph,
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NoItinerary, DSPRegs, DSPRegs>,
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ClearDefs;
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class PICK_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"pick.qb", int_mips_pick_qb,
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NoItinerary, DSPRegs, DSPRegs>,
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ClearDefs, UseDSPCtrl;
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class PICK_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"pick.ph", int_mips_pick_ph,
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NoItinerary, DSPRegs, DSPRegs>,
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ClearDefs, UseDSPCtrl;
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class BPOSGE32_DESC : BPOSGE32_DESC_BASE<"bposge32", NoItinerary>;
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// Extr
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@ -460,6 +589,22 @@ class SUBU_PH_DESC : ADDU_QB_DESC_BASE<"subu.ph", int_mips_subu_ph, NoItinerary,
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class SUBU_S_PH_DESC : ADDU_QB_DESC_BASE<"subu_s.ph", int_mips_subu_s_ph,
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NoItinerary, DSPRegs, DSPRegs>;
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// Comparison
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class CMPGDU_EQ_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.eq.qb",
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int_mips_cmpgdu_eq_qb,
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NoItinerary, CPURegs, DSPRegs>,
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IsCommutable;
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class CMPGDU_LT_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.lt.qb",
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int_mips_cmpgdu_lt_qb,
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NoItinerary, CPURegs, DSPRegs>,
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IsCommutable;
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class CMPGDU_LE_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.le.qb",
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int_mips_cmpgdu_le_qb,
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NoItinerary, CPURegs, DSPRegs>,
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IsCommutable;
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// Multiplication
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class MULQ_S_PH_DESC : ADDU_QB_DESC_BASE<"mulq_s.ph", int_mips_mulq_s_ph,
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NoItinerary, DSPRegs, DSPRegs>,
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@ -484,6 +629,21 @@ class DPSQX_SA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsqx_sa.w.ph">;
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class MULSA_W_PH_DESC : DPA_W_PH_DESC_BASE<"mulsa.w.ph">;
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// Precision reduce/expand
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class PRECR_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precr.qb.ph",
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int_mips_precr_qb_ph,
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NoItinerary, DSPRegs, DSPRegs>;
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class PRECR_SRA_PH_W_DESC : PRECR_SRA_PH_W_DESC_BASE<"precr_sra.ph.w",
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int_mips_precr_sra_ph_w,
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NoItinerary, DSPRegs,
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CPURegs>, ClearDefs;
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class PRECR_SRA_R_PH_W_DESC : PRECR_SRA_PH_W_DESC_BASE<"precr_sra_r.ph.w",
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int_mips_precr_sra_r_ph_w,
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NoItinerary, DSPRegs,
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CPURegs>, ClearDefs;
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// Pseudos.
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def BPOSGE32_PSEUDO : BPOSGE32_PSEUDO_DESC_BASE<int_mips_bposge32, NoItinerary>;
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@ -503,6 +663,10 @@ def ADDSC : ADDSC_ENC, ADDSC_DESC;
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def ADDWC : ADDWC_ENC, ADDWC_DESC;
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def MODSUB : MODSUB_ENC, MODSUB_DESC;
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def RADDU_W_QB : RADDU_W_QB_ENC, RADDU_W_QB_DESC;
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def PRECRQ_QB_PH : PRECRQ_QB_PH_ENC, PRECRQ_QB_PH_DESC;
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def PRECRQ_PH_W : PRECRQ_PH_W_ENC, PRECRQ_PH_W_DESC;
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def PRECRQ_RS_PH_W : PRECRQ_RS_PH_W_ENC, PRECRQ_RS_PH_W_DESC;
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def PRECRQU_S_QB_PH : PRECRQU_S_QB_PH_ENC, PRECRQU_S_QB_PH_DESC;
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def MULEU_S_PH_QBL : MULEU_S_PH_QBL_ENC, MULEU_S_PH_QBL_DESC;
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def MULEU_S_PH_QBR : MULEU_S_PH_QBR_ENC, MULEU_S_PH_QBR_DESC;
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def MULEQ_S_W_PHL : MULEQ_S_W_PHL_ENC, MULEQ_S_W_PHL_DESC;
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@ -527,6 +691,18 @@ def MADD_DSP : MADD_DSP_ENC, MADD_DSP_DESC;
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def MADDU_DSP : MADDU_DSP_ENC, MADDU_DSP_DESC;
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def MSUB_DSP : MSUB_DSP_ENC, MSUB_DSP_DESC;
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def MSUBU_DSP : MSUBU_DSP_ENC, MSUBU_DSP_DESC;
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def CMPU_EQ_QB : CMPU_EQ_QB_ENC, CMPU_EQ_QB_DESC;
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def CMPU_LT_QB : CMPU_LT_QB_ENC, CMPU_LT_QB_DESC;
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def CMPU_LE_QB : CMPU_LE_QB_ENC, CMPU_LE_QB_DESC;
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def CMPGU_EQ_QB : CMPGU_EQ_QB_ENC, CMPGU_EQ_QB_DESC;
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def CMPGU_LT_QB : CMPGU_LT_QB_ENC, CMPGU_LT_QB_DESC;
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def CMPGU_LE_QB : CMPGU_LE_QB_ENC, CMPGU_LE_QB_DESC;
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def CMP_EQ_PH : CMP_EQ_PH_ENC, CMP_EQ_PH_DESC;
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def CMP_LT_PH : CMP_LT_PH_ENC, CMP_LT_PH_DESC;
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def CMP_LE_PH : CMP_LE_PH_ENC, CMP_LE_PH_DESC;
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def PACKRL_PH : PACKRL_PH_ENC, PACKRL_PH_DESC;
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def PICK_QB : PICK_QB_ENC, PICK_QB_DESC;
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def PICK_PH : PICK_PH_ENC, PICK_PH_DESC;
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def BPOSGE32 : BPOSGE32_ENC, BPOSGE32_DESC;
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def EXTP : EXTP_ENC, EXTP_DESC;
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def EXTPV : EXTPV_ENC, EXTPV_DESC;
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@ -551,6 +727,9 @@ def ADDU_PH : ADDU_PH_ENC, ADDU_PH_DESC;
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def ADDU_S_PH : ADDU_S_PH_ENC, ADDU_S_PH_DESC;
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def SUBU_PH : SUBU_PH_ENC, SUBU_PH_DESC;
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def SUBU_S_PH : SUBU_S_PH_ENC, SUBU_S_PH_DESC;
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def CMPGDU_EQ_QB : CMPGDU_EQ_QB_ENC, CMPGDU_EQ_QB_DESC;
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def CMPGDU_LT_QB : CMPGDU_LT_QB_ENC, CMPGDU_LT_QB_DESC;
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def CMPGDU_LE_QB : CMPGDU_LE_QB_ENC, CMPGDU_LE_QB_DESC;
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def MULQ_S_PH : MULQ_S_PH_ENC, MULQ_S_PH_DESC;
|
||||
def DPA_W_PH : DPA_W_PH_ENC, DPA_W_PH_DESC;
|
||||
def DPS_W_PH : DPS_W_PH_ENC, DPS_W_PH_DESC;
|
||||
@ -561,6 +740,9 @@ def DPSX_W_PH : DPSX_W_PH_ENC, DPSX_W_PH_DESC;
|
||||
def DPSQX_S_W_PH : DPSQX_S_W_PH_ENC, DPSQX_S_W_PH_DESC;
|
||||
def DPSQX_SA_W_PH : DPSQX_SA_W_PH_ENC, DPSQX_SA_W_PH_DESC;
|
||||
def MULSA_W_PH : MULSA_W_PH_ENC, MULSA_W_PH_DESC;
|
||||
def PRECR_QB_PH : PRECR_QB_PH_ENC, PRECR_QB_PH_DESC;
|
||||
def PRECR_SRA_PH_W : PRECR_SRA_PH_W_ENC, PRECR_SRA_PH_W_DESC;
|
||||
def PRECR_SRA_R_PH_W : PRECR_SRA_R_PH_W_ENC, PRECR_SRA_R_PH_W_DESC;
|
||||
|
||||
}
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user