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Add a new SSA-based peephole optimizer which includes copy propagation and
folding of instructions into addressing modes. This creates lots of dead instructions, which are currently not deleted. It also creates a lot of instructions that the X86 backend currently cannot handle. :( git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@10275 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
parent
f2d2925452
commit
4537076ee8
@ -14,9 +14,12 @@
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#include "X86.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "Support/Statistic.h"
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using namespace llvm;
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namespace {
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Statistic<> NumPHOpts("x86-peephole",
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"Number of peephole optimization performed");
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struct PH : public MachineFunctionPass {
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virtual bool runOnMachineFunction(MachineFunction &MF);
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@ -34,9 +37,10 @@ bool PH::runOnMachineFunction(MachineFunction &MF) {
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for (MachineFunction::iterator BI = MF.begin(), E = MF.end(); BI != E; ++BI)
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for (MachineBasicBlock::iterator I = BI->begin(); I != BI->end(); )
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if (PeepholeOptimize(*BI, I))
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if (PeepholeOptimize(*BI, I)) {
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Changed = true;
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else
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++NumPHOpts;
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} else
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++I;
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return Changed;
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@ -133,3 +137,280 @@ bool PH::PeepholeOptimize(MachineBasicBlock &MBB,
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}
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}
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namespace {
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class UseDefChains : public MachineFunctionPass {
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std::vector<MachineInstr*> DefiningInst;
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public:
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// getDefinition - Return the machine instruction that defines the specified
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// SSA virtual register.
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MachineInstr *getDefinition(unsigned Reg) {
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assert(Reg >= MRegisterInfo::FirstVirtualRegister &&
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"use-def chains only exist for SSA registers!");
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assert(Reg - MRegisterInfo::FirstVirtualRegister < DefiningInst.size() &&
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"Unknown register number!");
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assert(DefiningInst[Reg-MRegisterInfo::FirstVirtualRegister] &&
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"Unknown register number!");
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return DefiningInst[Reg-MRegisterInfo::FirstVirtualRegister];
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}
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// setDefinition - Update the use-def chains to indicate that MI defines
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// register Reg.
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void setDefinition(unsigned Reg, MachineInstr *MI) {
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if (Reg-MRegisterInfo::FirstVirtualRegister >= DefiningInst.size())
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DefiningInst.resize(Reg-MRegisterInfo::FirstVirtualRegister+1);
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DefiningInst[Reg-MRegisterInfo::FirstVirtualRegister] = MI;
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}
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// removeDefinition - Update the use-def chains to forget about Reg
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// entirely.
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void removeDefinition(unsigned Reg) {
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assert(getDefinition(Reg)); // Check validity
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DefiningInst[Reg-MRegisterInfo::FirstVirtualRegister] = 0;
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}
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virtual bool runOnMachineFunction(MachineFunction &MF) {
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for (MachineFunction::iterator BI = MF.begin(), E = MF.end(); BI!=E; ++BI)
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for (MachineBasicBlock::iterator I = BI->begin(); I != BI->end(); ++I) {
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MachineInstr *MI = *I;
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = MI->getOperand(i);
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if (MO.isVirtualRegister() && MO.opIsDefOnly())
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setDefinition(MO.getReg(), MI);
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}
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}
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return false;
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}
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virtual void getAnalysisUsage(AnalysisUsage &AU) const {
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AU.setPreservesAll();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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virtual void releaseMemory() {
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std::vector<MachineInstr*>().swap(DefiningInst);
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}
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};
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RegisterAnalysis<UseDefChains> X("use-def-chains",
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"use-def chain construction for machine code");
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}
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namespace {
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Statistic<> NumSSAPHOpts("x86-ssa-peephole",
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"Number of SSA peephole optimization performed");
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/// SSAPH - This pass is an X86-specific, SSA-based, peephole optimizer. This
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/// pass is really a bad idea: a better instruction selector should completely
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/// supersume it. However, that will take some time to develop, and the
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/// simple things this can do are important now.
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class SSAPH : public MachineFunctionPass {
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UseDefChains *UDC;
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public:
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virtual bool runOnMachineFunction(MachineFunction &MF);
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bool PeepholeOptimize(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &I);
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virtual const char *getPassName() const {
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return "X86 SSA-based Peephole Optimizer";
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}
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/// Propagate - Set MI[DestOpNo] = Src[SrcOpNo], optionally change the
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/// opcode of the instruction, then return true.
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bool Propagate(MachineInstr *MI, unsigned DestOpNo,
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MachineInstr *Src, unsigned SrcOpNo, unsigned NewOpcode = 0){
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MI->getOperand(DestOpNo) = Src->getOperand(SrcOpNo);
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if (NewOpcode) MI->setOpcode(NewOpcode);
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return true;
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}
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/// OptimizeAddress - If we can fold the addressing arithmetic for this
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/// memory instruction into the instruction itself, do so and return true.
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bool OptimizeAddress(MachineInstr *MI, unsigned OpNo);
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/// getDefininingInst - If the specified operand is a read of an SSA
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/// register, return the machine instruction defining it, otherwise, return
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/// null.
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MachineInstr *getDefiningInst(MachineOperand &MO) {
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if (!MO.opIsUse() || !MO.isVirtualRegister()) return 0;
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return UDC->getDefinition(MO.getReg());
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}
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virtual void getAnalysisUsage(AnalysisUsage &AU) const {
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AU.addRequired<UseDefChains>();
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AU.addPreserved<UseDefChains>();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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};
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}
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FunctionPass *llvm::createX86SSAPeepholeOptimizerPass() { return new SSAPH(); }
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bool SSAPH::runOnMachineFunction(MachineFunction &MF) {
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bool Changed = false;
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bool LocalChanged;
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UDC = &getAnalysis<UseDefChains>();
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do {
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LocalChanged = false;
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for (MachineFunction::iterator BI = MF.begin(), E = MF.end(); BI != E; ++BI)
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for (MachineBasicBlock::iterator I = BI->begin(); I != BI->end(); )
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if (PeepholeOptimize(*BI, I)) {
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LocalChanged = true;
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++NumSSAPHOpts;
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} else
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++I;
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Changed |= LocalChanged;
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} while (LocalChanged);
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return Changed;
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}
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static bool isValidScaleAmount(unsigned Scale) {
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return Scale == 1 || Scale == 2 || Scale == 4 || Scale == 8;
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}
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/// OptimizeAddress - If we can fold the addressing arithmetic for this
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/// memory instruction into the instruction itself, do so and return true.
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bool SSAPH::OptimizeAddress(MachineInstr *MI, unsigned OpNo) {
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MachineOperand &BaseRegOp = MI->getOperand(OpNo+0);
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MachineOperand &ScaleOp = MI->getOperand(OpNo+1);
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MachineOperand &IndexRegOp = MI->getOperand(OpNo+2);
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MachineOperand &DisplacementOp = MI->getOperand(OpNo+3);
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unsigned BaseReg = BaseRegOp.hasAllocatedReg() ? BaseRegOp.getReg() : 0;
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unsigned Scale = ScaleOp.getImmedValue();
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unsigned IndexReg = IndexRegOp.hasAllocatedReg() ? IndexRegOp.getReg() : 0;
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bool Changed = false;
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// If the base register is unset, and the index register is set with a scale
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// of 1, move it to be the base register.
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if (BaseRegOp.hasAllocatedReg() && BaseReg == 0 &&
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Scale == 1 && IndexReg != 0) {
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BaseRegOp.setReg(IndexReg);
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IndexRegOp.setReg(0);
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return true;
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}
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// Attempt to fold instructions used by the base register into the instruction
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if (MachineInstr *DefInst = getDefiningInst(BaseRegOp)) {
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switch (DefInst->getOpcode()) {
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case X86::MOVir32:
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// If there is no displacement set for this instruction set one now.
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// FIXME: If we can fold two immediates together, we should do so!
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if (DisplacementOp.isImmediate() && !DisplacementOp.getImmedValue()) {
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if (DefInst->getOperand(1).isImmediate()) {
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BaseRegOp.setReg(0);
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return Propagate(MI, OpNo+3, DefInst, 1);
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}
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}
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break;
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case X86::ADDrr32:
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// If the source is a register-register add, and we do not yet have an
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// index register, fold the add into the memory address.
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if (IndexReg == 0) {
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BaseRegOp = DefInst->getOperand(1);
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IndexRegOp = DefInst->getOperand(2);
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ScaleOp.setImmedValue(1);
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return true;
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}
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break;
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case X86::SHLir32:
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// If this shift could be folded into the index portion of the address if
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// it were the index register, move it to the index register operand now,
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// so it will be folded in below.
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if ((Scale == 1 || (IndexReg == 0 && IndexRegOp.hasAllocatedReg())) &&
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DefInst->getOperand(2).getImmedValue() < 4) {
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std::swap(BaseRegOp, IndexRegOp);
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ScaleOp.setImmedValue(1); Scale = 1;
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std::swap(IndexReg, BaseReg);
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Changed = true;
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break;
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}
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}
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}
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// Attempt to fold instructions used by the index into the instruction
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if (MachineInstr *DefInst = getDefiningInst(IndexRegOp)) {
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switch (DefInst->getOpcode()) {
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case X86::SHLir32: {
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// Figure out what the resulting scale would be if we folded this shift.
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unsigned ResScale = Scale * (1 << DefInst->getOperand(2).getImmedValue());
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if (isValidScaleAmount(ResScale)) {
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IndexRegOp = DefInst->getOperand(1);
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ScaleOp.setImmedValue(ResScale);
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return true;
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}
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break;
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}
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}
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}
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return Changed;
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}
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bool SSAPH::PeepholeOptimize(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &I) {
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MachineInstr *MI = *I;
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MachineInstr *Next = (I+1 != MBB.end()) ? *(I+1) : 0;
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bool Changed = false;
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// Scan the operands of this instruction. If any operands are
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// register-register copies, replace the operand with the source.
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i)
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// Is this an SSA register use?
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if (MachineInstr *DefInst = getDefiningInst(MI->getOperand(i)))
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// If the operand is a vreg-vreg copy, it is always safe to replace the
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// source value with the input operand.
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if (DefInst->getOpcode() == X86::MOVrr8 ||
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DefInst->getOpcode() == X86::MOVrr16 ||
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DefInst->getOpcode() == X86::MOVrr32) {
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// Don't propagate physical registers into PHI nodes...
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if (MI->getOpcode() != X86::PHI ||
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DefInst->getOperand(1).isVirtualRegister())
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Changed = Propagate(MI, i, DefInst, 1);
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}
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// Perform instruction specific optimizations.
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switch (MI->getOpcode()) {
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// Register to memory stores. Format: <base,scale,indexreg,immdisp>, srcreg
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case X86::MOVrm32: case X86::MOVrm16: case X86::MOVrm8:
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case X86::MOVim32: case X86::MOVim16: case X86::MOVim8:
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// Check to see if we can fold the source instruction into this one...
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if (MachineInstr *SrcInst = getDefiningInst(MI->getOperand(4))) {
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switch (SrcInst->getOpcode()) {
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// Fold the immediate value into the store, if possible.
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case X86::MOVir8: return Propagate(MI, 4, SrcInst, 1, X86::MOVim8);
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case X86::MOVir16: return Propagate(MI, 4, SrcInst, 1, X86::MOVim16);
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case X86::MOVir32: return Propagate(MI, 4, SrcInst, 1, X86::MOVim32);
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default: break;
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}
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}
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// If we can optimize the addressing expression, do so now.
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if (OptimizeAddress(MI, 0))
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return true;
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break;
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case X86::MOVmr32:
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case X86::MOVmr16:
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case X86::MOVmr8:
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// If we can optimize the addressing expression, do so now.
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if (OptimizeAddress(MI, 1))
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return true;
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break;
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default: break;
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}
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return Changed;
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}
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@ -14,9 +14,12 @@
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#include "X86.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "Support/Statistic.h"
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using namespace llvm;
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namespace {
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Statistic<> NumPHOpts("x86-peephole",
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"Number of peephole optimization performed");
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struct PH : public MachineFunctionPass {
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virtual bool runOnMachineFunction(MachineFunction &MF);
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@ -34,9 +37,10 @@ bool PH::runOnMachineFunction(MachineFunction &MF) {
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for (MachineFunction::iterator BI = MF.begin(), E = MF.end(); BI != E; ++BI)
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for (MachineBasicBlock::iterator I = BI->begin(); I != BI->end(); )
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if (PeepholeOptimize(*BI, I))
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if (PeepholeOptimize(*BI, I)) {
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Changed = true;
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else
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++NumPHOpts;
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} else
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++I;
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return Changed;
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@ -133,3 +137,280 @@ bool PH::PeepholeOptimize(MachineBasicBlock &MBB,
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}
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}
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namespace {
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class UseDefChains : public MachineFunctionPass {
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std::vector<MachineInstr*> DefiningInst;
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public:
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// getDefinition - Return the machine instruction that defines the specified
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// SSA virtual register.
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MachineInstr *getDefinition(unsigned Reg) {
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assert(Reg >= MRegisterInfo::FirstVirtualRegister &&
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"use-def chains only exist for SSA registers!");
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assert(Reg - MRegisterInfo::FirstVirtualRegister < DefiningInst.size() &&
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"Unknown register number!");
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assert(DefiningInst[Reg-MRegisterInfo::FirstVirtualRegister] &&
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"Unknown register number!");
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return DefiningInst[Reg-MRegisterInfo::FirstVirtualRegister];
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}
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// setDefinition - Update the use-def chains to indicate that MI defines
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// register Reg.
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void setDefinition(unsigned Reg, MachineInstr *MI) {
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if (Reg-MRegisterInfo::FirstVirtualRegister >= DefiningInst.size())
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DefiningInst.resize(Reg-MRegisterInfo::FirstVirtualRegister+1);
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DefiningInst[Reg-MRegisterInfo::FirstVirtualRegister] = MI;
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}
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// removeDefinition - Update the use-def chains to forget about Reg
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// entirely.
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void removeDefinition(unsigned Reg) {
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assert(getDefinition(Reg)); // Check validity
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DefiningInst[Reg-MRegisterInfo::FirstVirtualRegister] = 0;
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}
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virtual bool runOnMachineFunction(MachineFunction &MF) {
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for (MachineFunction::iterator BI = MF.begin(), E = MF.end(); BI!=E; ++BI)
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for (MachineBasicBlock::iterator I = BI->begin(); I != BI->end(); ++I) {
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MachineInstr *MI = *I;
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = MI->getOperand(i);
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if (MO.isVirtualRegister() && MO.opIsDefOnly())
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setDefinition(MO.getReg(), MI);
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}
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}
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return false;
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}
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virtual void getAnalysisUsage(AnalysisUsage &AU) const {
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AU.setPreservesAll();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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virtual void releaseMemory() {
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std::vector<MachineInstr*>().swap(DefiningInst);
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}
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};
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RegisterAnalysis<UseDefChains> X("use-def-chains",
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"use-def chain construction for machine code");
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}
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namespace {
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Statistic<> NumSSAPHOpts("x86-ssa-peephole",
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"Number of SSA peephole optimization performed");
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/// SSAPH - This pass is an X86-specific, SSA-based, peephole optimizer. This
|
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/// pass is really a bad idea: a better instruction selector should completely
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/// supersume it. However, that will take some time to develop, and the
|
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/// simple things this can do are important now.
|
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class SSAPH : public MachineFunctionPass {
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UseDefChains *UDC;
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public:
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virtual bool runOnMachineFunction(MachineFunction &MF);
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bool PeepholeOptimize(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &I);
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virtual const char *getPassName() const {
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return "X86 SSA-based Peephole Optimizer";
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}
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/// Propagate - Set MI[DestOpNo] = Src[SrcOpNo], optionally change the
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/// opcode of the instruction, then return true.
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bool Propagate(MachineInstr *MI, unsigned DestOpNo,
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MachineInstr *Src, unsigned SrcOpNo, unsigned NewOpcode = 0){
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MI->getOperand(DestOpNo) = Src->getOperand(SrcOpNo);
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if (NewOpcode) MI->setOpcode(NewOpcode);
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return true;
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}
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/// OptimizeAddress - If we can fold the addressing arithmetic for this
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/// memory instruction into the instruction itself, do so and return true.
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bool OptimizeAddress(MachineInstr *MI, unsigned OpNo);
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/// getDefininingInst - If the specified operand is a read of an SSA
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/// register, return the machine instruction defining it, otherwise, return
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/// null.
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MachineInstr *getDefiningInst(MachineOperand &MO) {
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if (!MO.opIsUse() || !MO.isVirtualRegister()) return 0;
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return UDC->getDefinition(MO.getReg());
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}
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virtual void getAnalysisUsage(AnalysisUsage &AU) const {
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AU.addRequired<UseDefChains>();
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AU.addPreserved<UseDefChains>();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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};
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}
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FunctionPass *llvm::createX86SSAPeepholeOptimizerPass() { return new SSAPH(); }
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bool SSAPH::runOnMachineFunction(MachineFunction &MF) {
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bool Changed = false;
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bool LocalChanged;
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UDC = &getAnalysis<UseDefChains>();
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||||
|
||||
do {
|
||||
LocalChanged = false;
|
||||
|
||||
for (MachineFunction::iterator BI = MF.begin(), E = MF.end(); BI != E; ++BI)
|
||||
for (MachineBasicBlock::iterator I = BI->begin(); I != BI->end(); )
|
||||
if (PeepholeOptimize(*BI, I)) {
|
||||
LocalChanged = true;
|
||||
++NumSSAPHOpts;
|
||||
} else
|
||||
++I;
|
||||
Changed |= LocalChanged;
|
||||
} while (LocalChanged);
|
||||
|
||||
return Changed;
|
||||
}
|
||||
|
||||
static bool isValidScaleAmount(unsigned Scale) {
|
||||
return Scale == 1 || Scale == 2 || Scale == 4 || Scale == 8;
|
||||
}
|
||||
|
||||
/// OptimizeAddress - If we can fold the addressing arithmetic for this
|
||||
/// memory instruction into the instruction itself, do so and return true.
|
||||
bool SSAPH::OptimizeAddress(MachineInstr *MI, unsigned OpNo) {
|
||||
MachineOperand &BaseRegOp = MI->getOperand(OpNo+0);
|
||||
MachineOperand &ScaleOp = MI->getOperand(OpNo+1);
|
||||
MachineOperand &IndexRegOp = MI->getOperand(OpNo+2);
|
||||
MachineOperand &DisplacementOp = MI->getOperand(OpNo+3);
|
||||
|
||||
unsigned BaseReg = BaseRegOp.hasAllocatedReg() ? BaseRegOp.getReg() : 0;
|
||||
unsigned Scale = ScaleOp.getImmedValue();
|
||||
unsigned IndexReg = IndexRegOp.hasAllocatedReg() ? IndexRegOp.getReg() : 0;
|
||||
|
||||
bool Changed = false;
|
||||
|
||||
// If the base register is unset, and the index register is set with a scale
|
||||
// of 1, move it to be the base register.
|
||||
if (BaseRegOp.hasAllocatedReg() && BaseReg == 0 &&
|
||||
Scale == 1 && IndexReg != 0) {
|
||||
BaseRegOp.setReg(IndexReg);
|
||||
IndexRegOp.setReg(0);
|
||||
return true;
|
||||
}
|
||||
|
||||
// Attempt to fold instructions used by the base register into the instruction
|
||||
if (MachineInstr *DefInst = getDefiningInst(BaseRegOp)) {
|
||||
switch (DefInst->getOpcode()) {
|
||||
case X86::MOVir32:
|
||||
// If there is no displacement set for this instruction set one now.
|
||||
// FIXME: If we can fold two immediates together, we should do so!
|
||||
if (DisplacementOp.isImmediate() && !DisplacementOp.getImmedValue()) {
|
||||
if (DefInst->getOperand(1).isImmediate()) {
|
||||
BaseRegOp.setReg(0);
|
||||
return Propagate(MI, OpNo+3, DefInst, 1);
|
||||
}
|
||||
}
|
||||
break;
|
||||
|
||||
case X86::ADDrr32:
|
||||
// If the source is a register-register add, and we do not yet have an
|
||||
// index register, fold the add into the memory address.
|
||||
if (IndexReg == 0) {
|
||||
BaseRegOp = DefInst->getOperand(1);
|
||||
IndexRegOp = DefInst->getOperand(2);
|
||||
ScaleOp.setImmedValue(1);
|
||||
return true;
|
||||
}
|
||||
break;
|
||||
|
||||
case X86::SHLir32:
|
||||
// If this shift could be folded into the index portion of the address if
|
||||
// it were the index register, move it to the index register operand now,
|
||||
// so it will be folded in below.
|
||||
if ((Scale == 1 || (IndexReg == 0 && IndexRegOp.hasAllocatedReg())) &&
|
||||
DefInst->getOperand(2).getImmedValue() < 4) {
|
||||
std::swap(BaseRegOp, IndexRegOp);
|
||||
ScaleOp.setImmedValue(1); Scale = 1;
|
||||
std::swap(IndexReg, BaseReg);
|
||||
Changed = true;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Attempt to fold instructions used by the index into the instruction
|
||||
if (MachineInstr *DefInst = getDefiningInst(IndexRegOp)) {
|
||||
switch (DefInst->getOpcode()) {
|
||||
case X86::SHLir32: {
|
||||
// Figure out what the resulting scale would be if we folded this shift.
|
||||
unsigned ResScale = Scale * (1 << DefInst->getOperand(2).getImmedValue());
|
||||
if (isValidScaleAmount(ResScale)) {
|
||||
IndexRegOp = DefInst->getOperand(1);
|
||||
ScaleOp.setImmedValue(ResScale);
|
||||
return true;
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return Changed;
|
||||
}
|
||||
|
||||
bool SSAPH::PeepholeOptimize(MachineBasicBlock &MBB,
|
||||
MachineBasicBlock::iterator &I) {
|
||||
MachineInstr *MI = *I;
|
||||
MachineInstr *Next = (I+1 != MBB.end()) ? *(I+1) : 0;
|
||||
|
||||
bool Changed = false;
|
||||
|
||||
// Scan the operands of this instruction. If any operands are
|
||||
// register-register copies, replace the operand with the source.
|
||||
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i)
|
||||
// Is this an SSA register use?
|
||||
if (MachineInstr *DefInst = getDefiningInst(MI->getOperand(i)))
|
||||
// If the operand is a vreg-vreg copy, it is always safe to replace the
|
||||
// source value with the input operand.
|
||||
if (DefInst->getOpcode() == X86::MOVrr8 ||
|
||||
DefInst->getOpcode() == X86::MOVrr16 ||
|
||||
DefInst->getOpcode() == X86::MOVrr32) {
|
||||
// Don't propagate physical registers into PHI nodes...
|
||||
if (MI->getOpcode() != X86::PHI ||
|
||||
DefInst->getOperand(1).isVirtualRegister())
|
||||
Changed = Propagate(MI, i, DefInst, 1);
|
||||
}
|
||||
|
||||
|
||||
// Perform instruction specific optimizations.
|
||||
switch (MI->getOpcode()) {
|
||||
|
||||
// Register to memory stores. Format: <base,scale,indexreg,immdisp>, srcreg
|
||||
case X86::MOVrm32: case X86::MOVrm16: case X86::MOVrm8:
|
||||
case X86::MOVim32: case X86::MOVim16: case X86::MOVim8:
|
||||
// Check to see if we can fold the source instruction into this one...
|
||||
if (MachineInstr *SrcInst = getDefiningInst(MI->getOperand(4))) {
|
||||
switch (SrcInst->getOpcode()) {
|
||||
// Fold the immediate value into the store, if possible.
|
||||
case X86::MOVir8: return Propagate(MI, 4, SrcInst, 1, X86::MOVim8);
|
||||
case X86::MOVir16: return Propagate(MI, 4, SrcInst, 1, X86::MOVim16);
|
||||
case X86::MOVir32: return Propagate(MI, 4, SrcInst, 1, X86::MOVim32);
|
||||
default: break;
|
||||
}
|
||||
}
|
||||
|
||||
// If we can optimize the addressing expression, do so now.
|
||||
if (OptimizeAddress(MI, 0))
|
||||
return true;
|
||||
break;
|
||||
|
||||
case X86::MOVmr32:
|
||||
case X86::MOVmr16:
|
||||
case X86::MOVmr8:
|
||||
// If we can optimize the addressing expression, do so now.
|
||||
if (OptimizeAddress(MI, 1))
|
||||
return true;
|
||||
break;
|
||||
|
||||
default: break;
|
||||
}
|
||||
|
||||
return Changed;
|
||||
}
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user